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Scaling of indium gallium arsenide MOSFET into deep submicron regime

Dissertation
Author: Yanqing Wu
Abstract:
As the Si CMOS roadmap for scaling approaches its fundamental physics limits, alternatives have been extensively pursued for the future generation switches. III-V compound semiconductors, especially In-rich InGaAs, have attracted many efforts mainly because of its electron high mobility and velocity. Planar MOSFETs with gate lengths down to 150 nm have been fabricated and characterized. Record high extrinsic transconductance of 1.1 mS/μm has been achieved at V ds = 2.0 V with 5 nm Al2 O 3 as gate dielectric. gm can be further improved to 1.3 mS/μm by reducing the gate oxide thickness to 2.5 nm at Vds = 1.6 V. HBr pre-treatment, retro-grade structure and halo-implantation processes are introduced for the first time into III-V MOSFET to further improve high-k/ InGaAs interface quality and on-state/off-state performance of the devices. The key transistor scaling metrics such as subthreshold slope ( S.S. ), drain-induced barrier lowering (DIBL ), threshold voltage (VT ) of these treated devices are compared with channel lengths from 250 nm to 150 nm. To improve the short-channel effect (SCE) which severely affects the transistor output performance, the first well-behaved inversion-mode InGaAs FinFET with ALD Al2 O3 as gate dielectric has been demonstrated. Using a damage-free sidewall etching method, FinFETs with Lch down to 100 nm and WFin down to 40 nm are fabricated and characterized. Compared with the planar InGaAs MOSFETs at similar gate lengths, FinFETs have much better electro-static control and show improved output characteristics and less degradation at elevated temperatures. The SCE of III-V MOSFETs is greatly improved by the 3D structure.

TABLE OF CONTENTS Page LIST OF TABLES ............................................................................................................ vii

LIST OF FIGURES ......................................................................................................... viii

ABSTRACT ..................................................................................................................... xiii

1.

INTRODUCTION of III-V MOSFET .......................................................................... 1

1.1 Fundamentals of III-V Materials ........................................................................ 1

1.2 Overview of III-V MOSFET .............................................................................. 5

1.3 Introduction of Atomic Layer Deposition........................................................... 7

2.

FABRICATION PROCESS ........................................................................................ 10

2.1 Photo Lithography ............................................................................................ 10

2.2 Electron Beam Lithograph ................................................................................ 12

2.3 Wet and Dry Etching ........................................................................................ 15

2.3.1 Wet Etching ......................................................................................... 15

2.3.2 Dry Etching .......................................................................................... 18

3.

ALD INTEGRATION ON COMPOUND SEMICONDUCTORS ............................ 20

3.1 ALD Thin Film Breakdown Strength ............................................................... 20

3.2 GaN MOSCAP.................................................................................................. 26

3.3 GaN MOSFET .................................................................................................. 33

3.4 SiC MOSCAP ................................................................................................... 39

3.5 InP MOSFET .................................................................................................... 51

3.6 GaAs MOSFET on Si substrate ........................................................................ 64

4.

DEEP-SUBMICRON INGAAS MOSFET ................................................................. 71

4.1 High Performance Deep Sub-micron InGaAs .................................................. 71

vi

Page

4.2 New HBr Surface Treatment and Channel Engineering ................................... 76

4.3 Novel ultra shallow doping ............................................................................... 90

5.

INGAAS FINFET ....................................................................................................... 94

5.1 Introduction ....................................................................................................... 94

5.2 Device Structure and Process Flow .................................................................. 97

5.3 Results and Discussions .................................................................................. 100

6. SUBMMARY AND OUTLOOK ............................................................................. 108

LIST OF REFERENCES ................................................................................................ 109

VITA ............................................................................................................................... 124

vii

LIST OF TABLES Table Page 1.1 Electrical properties of important semiconductor materials ....................................... 5

2.1 Spin curve of photoresist AZ1500 series .................................................................. 11

2.2 Etching rate of III-V compound semiconductors ...................................................... 17

4.1 Scaling metrics of InGaAs MOSFET after 650 o C activation ................................... 74

viii

LIST OF FIGURES Figure Page 1.1 (a) crystal directions in zinc-blend crystal (b) band structure of In x Ga 1-x As. ............. 3

1.2 Bandgap versus lattice constant for all semiconductors. ............................................ 3

1.3 ALD system at Birck nanotechnology center, Purdue Univ. ...................................... 9

1.4 Schematic of ALD process of Al 2 O 3 deposition. ........................................................ 9

2.1 Spin curve of photoresist S1800 series from Shipley corp. ...................................... 11

2.2 PMMA spin curve from Microchem.com. ................................................................ 14

2.3 ZEP-520 spin curve from Zeonrex Electronic Chemicals Inc. ................................. 14

2.4 Cross section SEM image of InGaAs Fin structures after dry etching. .................... 19

2.5 Top view SEM image of the InGaAs Fin structures after dry etching. .................... 19

3.1 TEM image of GaAs with and without native oxide. ............................................... 21

3.2 Leakage current vs gate bias of 1.2nm and 6nm thick Al 2 O 3 on GaAs. ................... 21

3.3 (a) J Leak vs square root E for 12 Å and (b) 60 Å thick Al 2 O 3 on GaAs. ................... 23

3.4 Square root E m vs Temperature for Al 2 O 3 films from 12 Å to 60 Å. ....................... 25

3.5 Cross-section schematic view of GaN MOSCAP structure. ..................................... 29

3.6 Representative Photo-CV characteristics of GaN MOSCAP. .................................. 29

3.7 N D fitting from 1/C 2 vs gate voltage curve. .............................................................. 31

3.8 GaN Photo-CV after different annealing condition. ................................................. 31

ix

Figure Page 3.9 Dit estimation from the Photo-CV for different annealed samples. ......................... 33

3.10 Schematic view of GaN MOSFET and MESFET. ................................................. 35

3.11 Output characteristics of a typical GaN D-mode MOSFET. .................................. 35

3.12 Output characteristics of GaN MESFET with gate length of 2 micron. ................. 37

3.13 Transfer characteristics of GaN MESFET and MOSFET. ..................................... 37

3.14 Cross-section structure of schematic view of SiC MOSCAP. ................................ 41

3.15 Top view of SiC MOSCAP top-top configurations. ............................................... 41

3.16 CV characteristics comparison for different gate stacks. ........................................ 43

3.17 Photo-CV characteristics comparison for different gate stacks. ............................. 43

3.18 QSCV and 100 kHz CV at RT in dark. ................................................................... 45

3.19 QSCV and 100 kHz CV at 450 K in dark. ............................................................. 45

3.20 QSCV and 100 kHz CV at 450 K in light. ............................................................. 46

3.21 QSCV and 100 kHz CV at 450 K in light with different area. .............................. 46

3.22 100 KHz CV for capacitors with different areas. ................................................... 48

3.23 QSCV for capacitors with different areas. .............................................................. 48

3.24 Inversion response of delay time dependent QSCV under light at 450 K. ............. 50

3.25 Conductance plot of voltage and frequency for sample B at 450 K. ...................... 50

3.26 Cross section schematic view of the InP MOSFET. ............................................... 52

3.27 Output characteristics of a typical InP MOSFET with gate length of 0.75μm. ...... 52

3.28 Channel sheet resistance versus L Mask . .................................................................... 54

3.29 Transfer characteristics of a 20μm device at linear region. .................................... 54

3.30 V T extraction by different method. ......................................................................... 56

x

Figure Page 3.31 Transfer characteristics in linear and saturation regions. ........................................ 56

3.32 Mobility versus effective field with split-CV as inset. ........................................... 58

3.33 CV characteristics of different frequencies and quasi-static CV. ........................... 58

3.34 Output characteristics of a HfO 2 /InP MOSFET...................................................... 60

3.35 Split-CV characteristics of MOSFET with different gate oxide. ............................ 60

3.36 Transfer characteristics of InP MOSFET with different gate oxide. ...................... 61

3.37 Comparison of transconductance for transistors with different gate oxide. ........... 61

3.38 Drain current scalability with gate length down to 1μm. ........................................ 63

3.39 Effect of InP channel doping concentration difference. ......................................... 63

3.40 (a) Schematic cross section view (b) Cross section SEM of GaAs on Si. ............. 65

3.41 Output characteristics of a 10µm gate GaAs MOSFET on Si substrate. ................ 65

3.42 Transfer characteristics of the same transistor. ....................................................... 68

3.43 Effective mobility versus the electric field from the D-mode MOSFET. ............... 68

4.1 Cross-section schematic view and cross-section TEM of InGaAs MOSFET. ......... 72

4.2 Typical output characteristics of a 160nm InGaAs MOSFET. ................................. 72

4.3 Transfer characteristics of devices with activation of 750 o C (a) and 650 o C (b). ...... 74

4.4 Schematic view (a)Control (b)HBr-treated (c)Halo-implanted (d)Retrograde. ........ 77

4.5 Output characteristics of a 160nm HBr treated InGaAs MOSFET. ......................... 79

4.6 Transfer characteristics of the above transistor and intrinsic g m . ............................. 79

4.7 Log scale drain and source current versus gate voltage. ........................................... 80

4.8 I dss and g m scaling against gate length at V DD of 2.0 V. ............................................ 80

4.9 Comparison of I dss scaling against L ch for two different EOT. ................................. 82

xi

Figure Page 4.10 Comparison of Peak g m scaling against L ch for two different EOT. ....................... 82

4.11 Comparison of S.S. scaling for two different EOT in saturation region. ................ 83

4.12 Comparison of DIBL scaling for two different EOT. ............................................. 83

4.13 Comparison of V T scaling for two different EOT in saturation region. ................. 85

4.14 Comparison of on-off ratio scaling of two different EOT in saturation region. ..... 85

4.15 Comparison of I dss for four different treated samples. ............................................ 86

4.16 Comparison of g m for four different treated samples. ............................................. 86

4.17 Comparison of DIBL for four different treated samples. ....................................... 88

4.18 Comparison of S.S. for four different treated samples. .......................................... 88

4.19 Comparison of V T for four different treated samples. ............................................ 89

4.20 Comparison of on-off ratio for four different treated samples. .............................. 89

4.21 Cross section schematic view of the S-doped InGaAs MOSFET........................... 91

4.22 Comparison of gate capacitance for S-activated and control devices. .................... 91

4.23 Comparison of output performance for S-activated and control sample. ............... 92

4.24 Comparison of transfer characteristics for S-activated and control sample. .......... 92

5.1 Cross section schematic view of the InGaAs FinFET structure. .............................. 95

5.2 SEM images of finished device (a), (b) and after dry etching (c), (d). ..................... 95

5.3 Process flow of InGaAs FinFET ............................................................................... 96

5.4 Output Performance of a 100nm planar InGaAs FET. ............................................. 98

5.5 Output performance of a 100nm InGaAs FinFET with W Fin =40nm. ....................... 98

5.6 Comparison of transfer characteristics for planar and FinFET devices. .................. 99

5.7 T-dependent transfer characteristics of a 100nm FinFET with W Fin =40nm ............. 99

xii

Figure Page 5.8 SS comparison of planar and FinFET devices with different L ch and W Fin . ........... 101

5.9 SS of FinFET devices with different W Fin / L ch ratio. ............................................. 101

5.10 DIBL of planar and FinFET devices with different L ch and W Fin . ........................ 102

5.11 DIBL of FinFET devices with different W Fin / L ch ratio. ...................................... 102

5.12 Comparison of V Tsat for planar and FinFET devices. .......................................... 104

5.13 On-off ratio versus W Fin /L ch for for FinFETs devices. ........................................ 104

5.14 T-dependent comparison of SS for planar with FinFETs at V ds =0.05V. ............. 105

5.15 T-dependent comparison of SS for planar with FinFETs at V ds =0.05V. ............. 105

5.16 T-dependent comparison of DIBL for planar with FinFETs. .............................. 107

5.17 T-dependent comparison of V Tsat for planar with FinFETs. ................................ 107

xiii

ABSTRACT Wu, Yanqing. Ph. D., Purdue University, December, 2009. Scaling of InGaAs MOSFET into Deep Submicron Regime. Major Professor: Peide Ye.

As the Si CMOS roadmap for scaling approaches its fundamental physics limits, alternatives have been extensively pursued for the future generation switches. III-V compound semiconductors, especially In-rich InGaAs, have attracted many efforts mainly because of its electron high mobility and velocity. Planar MOSFETs with gate lengths down to 150 nm have been fabricated and characterized. Record high extrinsic transconductance of 1.1 mS/µm has been achieved at V ds = 2.0 V with 5 nm Al 2 O 3 as gate dielectric. g m can be further improved to 1.3 mS/µm by reducing the gate oxide thickness to 2.5 nm at V ds = 1.6 V. HBr pre-treatment, retro-grade structure and halo-implantation processes are introduced for the first time into III-V MOSFET to further improve high- k/InGaAs interface quality and on-state/off-state performance of the devices. The key transistor scaling metrics such as subthreshold slope (S.S.), drain-induced barrier lowering (DIBL), threshold voltage (V T ) of these treated devices are compared with channel lengths from 250 nm to 150 nm. To improve the short-channel effect (SCE) which severely affects the transistor output performance, the first well-behaved inversion-mode InGaAs FinFET with ALD Al 2 O 3 as gate dielectric has been demonstrated. Using a damage-free sidewall etching method, FinFETs with L ch down to 100 nm and W Fin down to 40 nm are fabricated and characterized. Compared with the planar InGaAs MOSFETs at similar gate lengths, FinFETs have much better electro- static control and show improved output characteristics and less degradation at elevated temperatures. The SCE of III-V MOSFETs is greatly improved by the 3D structure.

1

1. INTRODUCTION OF III-V MOSFET 1.1 Fundamentals of III-V Materials The building block for the now hundred-billion dollar semiconductor industry first started at the year 1947 when first pointed-contacted transistor was invented. The Si CMOS has since begun its journey of the ruthless scaling in pursuit of higher speed and less power consumption following the later proposed “Moore’s Law” by Gordon Moore. The need to meet the requirement on the International Technology Roadmap for Semiconductors (ITRS) [1] has become more and more challenging since the technology node enters the deep-submicrometer region. The quantum tunneling through the thinner and thinner silicon dioxide has been relieved by implementing the high-kappa / metal gate configuration [2]. However, the scaling faces much bigger challenge by entering the 22nm node generation and beyond. By considering both lithography cost and resolution requirement, current lithography techniques and research-oriented Electron-beam lithography, as well as nano-imprinting, all have certain drawbacks which withholds their potential. Even the most promising EUV tool is now still in debating and has been delayed for the current technology node. Beyond the manufacturing challenge, the transistor performance will exhibit a huge gap between the projected metrics and the real output around 15nm node. Novel concepts for digital applications such as carbon nanotube [3-12], Si nanowire FETs [13-15], resonant tunneling FET [16-18], single electron transistors [19-22] and molecular devices [23-24] have been studied and researched extensively in order to tackle the grand challenge of Si CMOS scaling. Among all potential candidates, III-V has emerged as one of the most promising candidate because of its much higher mobility and electron velocity. Unlike Si, many of the binary and ternary groups of III-V are direct bandgap. The ability to emit and absorb

2

photons efficiently enables very promising applications in terms of optical applications like light-emitting diode (LED) and high efficiency photovoltaic devices. The blue LED made from GaN was introduced not long ago and remains one of the most important inventions for general lighting applications. GaAs based solar cells have much better quantum efficiency than silicon and other materials so far. III-V compound semiconductors usually have zinc-blend crystals, which is similar to the diamond structure of silicon, with the difference two types of atoms instead of only one. The typical crystal orientations and band structures are shown in Fig. 1.1 (adopted from HTTP://WWW.IOFFE.RSSI.RU/SVA/NSM/SEMICOND/GAINAS/BANDSTR.H TML ). As can be seen from Fig. 1.1(b), electrons in valence band can jump to the conductance band directly provided there is enough photon energy, without the requirement of available Phonon. Thus the possibility of band to band generation and recombination processes is much larger than that of those indirect bandgap semiconductors like Si. Also notice here that there is an L-valley on the <111> direction and it has larger effective mass. Many III-V semiconductors like GaAs have this heavier electron valley, which is the physical reason of the so-called “Gunn effect”. When electrons gain enough energy, it will jump from the primary valley to this heavier mass valley and cause the drop of the mobility. This needs to be avoided for the normal applications which take advantage of III-V mostly for their high mobility. However, special engineering can be done to use this effect and form a type of device like “Gunn diode” for particular use. Group III and group V combination will result in many types of compound semiconductors. The availability of different mole fraction combinations provides almost infinite choice in the III-V compound semiconductor family in terms of bandgap, effective mass and lattice constant [25]. Researchers can always find some routes from one semiconductor to another and this makes heterogeneous integration of III-V on Si possible by gradually changing the buffer material within the lattice stress induced defects and finally reach the target material. This is especially important in terms of cost and scale. Only limited thickness and area of III-V material are needed on the silicon substrate, while fully utilizing the mechanical properties and thermal properties of silicon wafers.

3

Fig. 1.1 (a) crystal directions in zinc-blend crystal (b) band structure of In x Ga 1-x As.

Fig. 1.2 Bandgap versus lattice constant for all semiconductors.

4

The major electrical properties of important semiconductors are listed in Table 1.1. The electron mobility of In-rich InGaAs is around 14000 cm 2 V -1 s -1 , and this is almost 10 times higher than that of Si, which is 1450 cm 2 V -1 s -1 . This is usually quoted as low-field mobility, which dominates in the mobility region at low transverse electric field. However, in modern CMOS applications, the most important metric is electron velocity, instead of the mobility. The conventional velocity is called saturation velocity, as the devices usually operate at the saturation region, where electric field is strong enough to accelerate the electrons to its highest speed. In today’s deeply scaleed transistor generation (65nm and beyond), the channel is so short that the electrons can travel from the source to drain without any scattering, meaning the channel length is smaller than the electron mean free path. Another advantage of InGaAs is the small adjustable bandgap from 0.35eV of InAs to 1.42eV of GaAs. The future generations generally require less power consumption, while retaining similar or even better output performance. For In-rich InGaAs devices, the supply voltage can be reduced to almost to half of that of silicon devices at comparable generation. For some of the high electron mobility transistors (HEMTs) demonstrated recently, the supply voltage is very low at the range of 0.5 V. As discussed above, the III-V semiconductors, especially In-rich InGaAs, have great advantage in terms of N-type transistor operation for the logic applications and RF applications. Although some complicated method like molecule beam epitaxy (MBE) is needed to grown high quality III-V materials, various work is going on to reduce the cost and equipment requirement, while keeping the high product quality. The unique property of varying lattice constant by varying mole fraction in the compound has paved the way for the integration of expensive III-V to the mass-produced Si wafers as shown to Fig. 1.2 (http://web.tiscali.it/decartes/phd_html/III-Vms-latgap.png)

5

Table 1.1 Electrical properties of important semiconductor materials 1.42 1.34 1.12 0.75 0.66 0.35 0.17 E g (eV) 2 2.4 1 2.7 1 4.0 5.0 V sat (10 7 cm/s) 0.066 0.08 0.19 0.041 0.082 0.023 0.014 m n (m 0 ) 1.42 200 450 300 1900 0.35 850 µ p (cm 2 /V·s) 8500 5400 1450 14000 3900 25000 77000 µ n (cm 2 /V·s) GaAs InP Si In 0.53 Ga 0.47 As Ge InAs InSb @ 300K 1.42 1.34 1.12 0.75 0.66 0.35 0.17 E g (eV) 2 2.4 1 2.7 1 4.0 5.0 V sat (10 7 cm/s) 0.066 0.08 0.19 0.041 0.082 0.023 0.014 m n (m 0 ) 1.42 200 450 300 1900 0.35 850 µ p (cm 2 /V·s) 8500 5400 1450 14000 3900 25000 77000 µ n (cm 2 /V·s) GaAs InP Si In 0.53 Ga 0.47 As Ge InAs InSb @ 300K

1.2 Overview of III-V MOSFET The early demonstration of depletion-mode GaAs MOSFET in about four decades ago has inspired many research efforts in this area since then. However, unlike in RF applications, depletion-mode devices are unsuitable for digital applications which require the normally-off operations. Thus enhancement-mode III-V MOSFET has became the focus of research efforts. One of the biggest challenges for III-V MOSFET is to find the right oxide. Unlike SiO 2 on Si, which is now regarded as a almost perfect system of which the interface trap density has been lowered to the mid-10 10 eV -1 cm -2 , the native oxide of III-V has much larger amount of interface traps which would result in Fermi- level pinning. The major causes are believed to be interfacial lattice defects, stoichiometry perturbation and unstable native oxide. The lack of high quality, thermodynamically stable insulators on III-V has made the MOS type normally-off transistor very difficult to realize. Significant progress has been made since the past decade on inversion-type enhancement-mode InGaAs MOSFET using high-k gate dielectrics. The demonstrated high-k dielectrics include in-situ MBE Ga 2 O 3 (Gd 2 O 3 ), ex- situ ALD Al 2 O 3 , HfO 2 , HfAlO, ZrO 2 . Although the interface quality is still not comparable with the SiO 2 /Si system, the trap level has improved greatly and the best value now achieved is around mid-10 11 eV -1 cm -2 . To the surprise of many, with the relatively high interface trap density, InGaAs can achieve very high output performance with more than 1A/mm drain current, and more than 1S/mm transconductance. Some research shows that high performance is possible at high trap level, provided the trap type

6

is donor-like, which will not affect much of the surface potential and minority carrier generation. The similar version of Si MOSFET for III-V transistors is the previously discussed inversion-type devices. This type of devices employs the similar concept and processes as silicon. The device physics and transport mechanisms are based on gate controlled inverted minority carrier travelling from source and drain. The two major factors directly determining the output performance are inversion carrier density and travelling velocity. The interface traps will have negative impact on both parameters. Part of the trap levels will participate in the charging-discharging process and thus contribute to the total channel capacitance with an additional trap capacitance. It will reduce the gate controlled mobile inversion charge density and the effectiveness of the gate control mainly reflected by how fast the channel will be switched on. Although some of the studies showed that only one type of the traps will contribute negatively on this aspect, it is yet to be understood how to distinguish the specific trap type and eliminate its density. While In-situ methods like MBE grown oxide under ultra-high vacuum will minimize the trap level, it is not compatible with the modern CMOS process in terms of the cost and availability. One of the most promising ways of ex-situ gate stack growth method is ALD, which has already been adopted in the 45nm-node process by Intel. Novel HBr/Sulfur-based wet treatment has been proved to improve the overall quality of the interface by boosting the transistor output performance and reduction of the short channel effect in deep sub-micron regime. The detailed process and output characteristics of the improved devices will be discussed in the following chapters. Another key metric that largely determines the output current is the electron travelling velocity, which is the saturation velocity for long channel devices and is modified as injection velocity for ultra-short channel devices. The fundamental material property for velocity is the mobility, which mostly refers to low-field mobility. The carrier mobility is inversely proportional to the carrier effective mass, electron or hole as the following equation. * m q m τ µ = (1.1)

7

Where m τ is scattering time constant and * m is the effective mass of the carrier. III-V materials usually have much smaller effective mass than Si which can is shown in Table 1.1. Also, one advantage of the InGaAs material is the smaller bandgap which will require less surface potential change to reach strong inversion. It has the intrinsic advantage for the future low power supply applications. Another type of III-V devices which also attracts tremendous attention is the high electron mobility transistor (HEMT) [26-28]. Unlike inversion-type devices, HEMT relies on the majority carriers to conduct the current from source to drain. The enhancement-mode HEMT can be realized by depleting the carriers at channel regions at zero gate bias and then being brought back by gate bias. HEMT is conventionally used for RF applications, due to their very high electron velocity. Since the carriers in the channel are formed in the quantum well and are screened from any scattering from the gate interface, there is very little degradation of mobility. However, HEMT has some disadvantages in scaling. One big problem is the gate leakage since most HEMT structures has a very thin gate dielectric in order to achieve the high performance. However, due to the small bandgap of this dielectric, which are mostly wide-bandgap III- V semiconductors, the gate leakage is severe. Also the scaling potential for HEMT is limited because this dielectric cannot be thinned much further in order to boost performance. Using high-k dielectric on top of the existing dielectric can solve the leakage problem to a certain degree, but still faces the problem of further EOT reduction. Also, the typical HEMT structures are not self-aligned, which cause serious problem of continuous scaling. 1.3 Introduction of Atomic Layer Deposition ALD is a layer-by layer process with precise surface controlled during the deposition of thin films with atomic layer accuracy. Similarly like chemical vapor deposition (CVD) methods, ALD is based upon the chemical reaction on the surface. The main difference is that ALD relies on two self-limiting half reactions that provide part of the compound that occur on the surface of the substrate. The deposition process produces

8

one atomic layer each cycle through the alternative pulsing of precursors. No pinholes will be produced on the surface thanks to excellent step coverage and dense films provided by surface-controlled growth mechanism of ALD. Well-controlled extremely thin and uniform nanometer scale films can be achieved by ALD. Over the last few years, ALD applications have developed rapidly in the areas of high-k gate dielectrics and back- end interconnects. Recently high-k and metal gate structure have been adopted by Intel for the next generation CPU. ALD has now entered a new era of supporting the digital IC process lines. The ALD used here is an ASM F-120. A cycle refers to a sequence of an exposure of one precursor for a certain time, Nitrogen purge, an exposure of another precursor for a certain time and Nitrogen purge. Each of the cycle corresponds to the growth of one layer of the film with thickness of about 0.1nm. Since the process is self- limiting, the precise growth rate could be recorded with the number of cycles. By adjusting the exposure time and temperature, high aspect ratio surface structures such as deep trenches or high pillars can be conformably coated. This is highly desirable for some specific applications in bio-related areas or deep-trench related 3D nanostructures. Atomic force microscopy (AFM) images of ALD Al 2 O 3 reveals pinhole-free surface coating with nearly the same surface roughness as the substrates which include most semiconductors, oxides nitrides and various metals. This layer by layer growth mechanism is suitable for most cases with the exception of certain materials such as carbon nanotubes and graphene since there are no free dangling bonds on the top surface for the reactant to absorb. Some technique such as DNA coating, or TMA/NO 2

Full document contains 142 pages
Abstract: As the Si CMOS roadmap for scaling approaches its fundamental physics limits, alternatives have been extensively pursued for the future generation switches. III-V compound semiconductors, especially In-rich InGaAs, have attracted many efforts mainly because of its electron high mobility and velocity. Planar MOSFETs with gate lengths down to 150 nm have been fabricated and characterized. Record high extrinsic transconductance of 1.1 mS/μm has been achieved at V ds = 2.0 V with 5 nm Al2 O 3 as gate dielectric. gm can be further improved to 1.3 mS/μm by reducing the gate oxide thickness to 2.5 nm at Vds = 1.6 V. HBr pre-treatment, retro-grade structure and halo-implantation processes are introduced for the first time into III-V MOSFET to further improve high-k/ InGaAs interface quality and on-state/off-state performance of the devices. The key transistor scaling metrics such as subthreshold slope ( S.S. ), drain-induced barrier lowering (DIBL ), threshold voltage (VT ) of these treated devices are compared with channel lengths from 250 nm to 150 nm. To improve the short-channel effect (SCE) which severely affects the transistor output performance, the first well-behaved inversion-mode InGaAs FinFET with ALD Al2 O3 as gate dielectric has been demonstrated. Using a damage-free sidewall etching method, FinFETs with Lch down to 100 nm and WFin down to 40 nm are fabricated and characterized. Compared with the planar InGaAs MOSFETs at similar gate lengths, FinFETs have much better electro-static control and show improved output characteristics and less degradation at elevated temperatures. The SCE of III-V MOSFETs is greatly improved by the 3D structure.