# Low Power Design Techniques for Analog-to-Digital Converters in Submicron CMOS

T ABLE OF CONTENTS P age 1 INTRODUCTION....................................................1 1.1 Motivation.......................................................1 1.2 Contribution.....................................................3 1.3 Organization.....................................................3 2 AMPLIFIERS IN SWITCHED-CAPACITOR ANALOG-TO-DIGITAL CONVERTERS.......................................................4 2.1 Eﬀect of Finite Ampliﬁer Gain...................................4 2.1.1 Sample-and-Hold........................................5 2.1.2 Multiplying Digital-to-Analog Converter..................6 2.1.3 Integrator...............................................7 2.2 ADC Architectures..............................................9 2.2.1 Flash ADC..............................................9 2.2.2 Two-step ADC..........................................11 2.2.3 Pipelined ADC..........................................12 2.2.4 Delta-Sigma ADC.......................................15 3 LOWPOWER GAIN-ENHANCEMENT TECHNIQUES.............19 3.1 Introduction.....................................................19 3.2 Precise Op-amp Gain Technique.................................20 3.3 Replica Gain Enhancement......................................21 3.4 Correlated Double Sampling.....................................23 3.4.1 Predictive Correlated Double Sampling...................24 3.4.2 Time-Shifted Correlated Double Sampling................28 3.4.3 Time-Aligned/Split-Capacitor Correlated Double Sampling 29 3.5 Correlated Level Shifting.........................................30

T ABLE OF CONTENTS (Continued) P age 4 CROSS-COUPLED CORRELATED LEVEL SHIFTING PIPELINED ADC.................................................................33 4.1 Introduction.....................................................33 4.2 Cross-Coupled CLS Technique...................................34 4.2.1 Sensitivity to DC gain variations.........................36 4.2.2 Loop characteristics and settling.........................38 4.3 Architecture.....................................................40 4.4 Circuit Implementation..........................................41 4.4.1 No SAH Input Stage.....................................41 4.4.2 2.5bit/stage MDAC......................................42 4.4.3 Opamp..................................................45 4.4.4 Sampling Switch.........................................46 4.4.5 SubADC................................................46 4.4.6 Clock Generator.........................................49 4.5 Simulation Results...............................................51 5 CORRELATED LEVEL SHIFTING INTEGRATOR..................53 5.1 Correlated Level Shifting Integrator..............................53 5.2 Application to ∆Σ Modulators...................................56 5.3 Simulation Results...............................................57 6 ALTERNATIVE TO AMPLIFIERS IN SC CIRCUITS................59 6.1 Introduction.....................................................59 6.2 Zero-Crossing-Based Circuits.....................................60 6.3 Oﬀset Compensation in ZCBCs..................................62 6.3.1 Coarse-ﬁne charging.....................................62 6.3.2 Input referred oﬀset compensation........................63

T ABLE OF CONTENTS (Continued) P age 6.4 Nonlinearities in the Overshoot Error............................64 6.5 Conceptual Zero-Crossing-Based Integrator......................65 6.6 Multi Rate Charging Scheme.....................................66 6.7 Modulator Architecture..........................................68 6.8 Circuit Implementation..........................................70 6.8.1 Switched Resistor Current Sources.......................70 6.8.2 Zero-Crossing Detector...................................70 6.8.3 Quantizer................................................71 6.8.4 Reset Pulse Generation..................................72 6.9 Measurement Results............................................72 7 CONCLUSION.......................................................76 8 APPENDIX..........................................................78 BIBLIOGRAPHY........................................................80

LIST OF FIGURES Figure P age 1.1 2009 International Technology Roadmap for Semiconductors.....1 2.1 Representation of operational transconductance ampliﬁer........4 2.2 Flip-around sample-and-hold....................................6 2.3 Flip-around multiplying digital-to-analog converter.............7 2.4 Integrator with shared input and DAC capacitor................8 2.5 2-bit ﬂash ADC................................................10 2.6 Two-step ADC.................................................11 2.7 Pipelined ADC.................................................13 2.8 Eﬀect of gain error in pipelined ADC linearity...................15 2.9 Delta-sigma ADC...............................................16 2.10 Eﬀect of ampliﬁer gain on noise shaping.........................17 2.11 Two-stage MASH ADC.........................................18 3.1 POG ﬂip-around MDAC........................................20 3.2 POG integrator.................................................21 3.3 Replica gain enhanced SAH.....................................22 3.4 Replica gain enhanced gain stage................................23 3.5 Haug CDS (a)gain stage and (b)integrator......................25 3.6 Larson CDS (a)gain stage and (b)integrator.....................27 3.7 Nagaraj CDS (a)gain stage and (b)integrator....................27 3.8 Time-shifted CDS..............................................29 3.9 Correlated Level Shifting MDAC................................31 3.10 CLS MDAC with two-stage ampliﬁer............................32 4.1 Cross-Coupled CLS MDAC.....................................34

LIST OF FIGURES (Continued) Figure P age 4.2 Cross-Coupled CLS MDAC - Estimation........................35 4.3 Cross-Coupled CLS MDAC - Level Shifting.....................35 4.4 Sensitivity of loop gain to DC gain variation.....................37 4.5 Eﬀect of C P on Accuracy.......................................38 4.6 Settling response of CLS MDAC................................40 4.7 Pipelined ADC block diagram...................................42 4.8 SAH-less sampling conﬁguration................................43 4.9 2.5bit MDAC...................................................44 4.10 Opamp Schematic..............................................45 4.11 Bootstrapped switch............................................46 4.12 7 level quantizer................................................47 4.13 3 level DAC....................................................48 4.14 2.5bit decoder..................................................48 4.15 Comparator schematics.........................................49 4.16 Four phase clock generator......................................50 4.17 Clock phases...................................................50 4.18 Non-overlapping clock generator................................50 4.19 Chip Micrograph...............................................51 4.20 ADC output spectrum..........................................52 5.1 CLS Integrator.................................................54 5.2 CLS Integrator.................................................55 5.3 2-0 MASH......................................................56 5.4 Integrator transfer functions....................................57

LIST OF FIGURES (Continued) Figure P age 5.5 Output spectrum of modulator..................................58 6.1 Comparator-based MDAC......................................60 6.2 Eﬀect of Coarse-ﬁne on overshoot...............................62 6.3 Zero-crossing-based Integrator..................................65 6.4 Multi-rate charging scheme.....................................67 6.5 Overshoot minimized ZCB integrator............................68 6.6 Zero-crossing-based integrator...................................69 6.7 2nd order feedforward ∆Σ modulator...........................69 6.8 Zero-crossing detector...........................................71 6.9 Zero-crossing detector circuit....................................71 6.10 Rising-edge detector............................................72 6.11 Output spectrum of modulator at 1.1V..........................73 6.12 Output spectrum of modulator at 1.2V..........................73 6.13 SNR vs input level at 1.1V......................................74 6.14 Chip micrograph................................................74

LIST OF TABLES T able P age 4.1 Performance summary..........................................52 6.1 Performance summary..........................................75 8.1 Gain enhancement in gain stages................................78 8.2 Gain enhancement in integrators................................79

LOWPOWER DESIGN TECHNIQUES FOR ANALOG-TO-DIGITAL CONVERTERS IN SUBMICRON CMOS CHAPTER 1.INTRODUCTION 1.1 Motivation 2008 2010 2012 2014 2016 2018 2020 2022 2024 2026 0 0.5 1 Power Supply [V]

Power Supply 2008 2010 2012 2014 2016 2018 2020 2022 2024 2026 0 20 40 Gate Length [nm]

Gate Length Figure 1.1:2009 International Technology Roadmap for Semiconductors. In 1965,Gordon Moore predicted that the number of transistors that can be placed in an integrated circuit will increase at a rate of roughly a factor of two

2 p er year [1].Ten years later,he modiﬁed his prediction to forecast doubling of the number of transistors every two years.This prediction became more of a guideline for driving the cost of electronics down [2] and the semiconductor industry has been adhering to it since.To achieve the steep increase in density,the dimensions of the transistor have to be scaled down accordingly.This has to accompanied with a reduction in supply voltages to reduce the stress on the transistors and improve reliability.The 2009 International Technology Roadmap for Semiconductors [3] forecast of the transistor gate length and corresponding power supply is shown in Fig.1.1.It predicts that the supply voltage for low operating power processes will decrease to 0.6V with a gate length of about 10nm by 2021. While this decrease in size and lower supply voltage lead to faster and lower power digital circuit blocks,their analog counterparts do not see the same bene- ﬁts [4].This is because the decrease in supply voltages results in limited signal swing and for that matter signal-to-noise ratio.Moreover,the intrinsic gain as well as transistor matching,decreases with each technology scaling.As a result complex design techniques have to be employed to design high performance analog and mixed-signal circuits in advanced processes. To design low power analog-to-digital (ADC) circuits in submicron CMOS, the goal is to be able to achieve high performance while using simple building blocks.The most power-consuming building block in switched-capacitor ADC circuits is the ampliﬁer.High performance ADCs require ampliﬁers with high DC gain and bandwidth,which are diﬃcult to achieve in submicron processes without sacriﬁcing power eﬃciency.There have been several techniques proposed to realize high eﬀective ampliﬁer gain using low gain ampliﬁer circuits,but their susceptibility to noise makes them unattractive for high performance ADCs.

3 1.2 Contribution This work is aimed at developing design techniques that realize low power switch-capacitor circuits without increasing noise.The techniques include: a) An improved Correlated Level Shifting (CLS) technique that allows the use of low gain single stage ampliﬁers to realize very high eﬀective loop gain. b) A CLS integrator that needs only two phases for its operation and oﬀers the possibility of removing the phase error of the integrator. c) A zero-crossing-based integrator that has the promise of becoming a low power alternative to traditional ampliﬁers,especially in deep submicron processes. 1.3 Organization The rest of this thesis is organized as follows.Chapter 2 discusses the eﬀect ﬁnite ampliﬁer DC gain has on major switched-capacitor building blocks and how these eﬀects limit the performance of several ADC structures.Chapter 3 surveys past techniques and proposes new ones to achieve gain enhancement in switched- capacitor building blocks.The design of a pipelined ADC using the improved CLS technique and a low phase error CLS integrator are presented in Chapters 4 and 5 respectively.The design of a zero-crossing based delta-sigma ADC is explored in Chapter 6.A summary of the research accomplishments concludes the thesis as Chapter 7.

4 CHAPTER 2.AMPLIFIERS IN SWITCHED-CAPACITOR ANALOG-TO-DIGITAL CONVERTERS 2.1 Eﬀect of Finite Ampliﬁer Gain

Figure 2.1:Representation of operational transconductance ampliﬁer Switched-capacitor circuits are notable for their insensitivity to absolute ca- pacitor values.The simplest realization of the circuits involve a set of capacitors that are charged to a particular voltage,then the charge is transferred to another set of capacitors.Gain or attenuation is achieved by appropriately sizing the two sets of capacitors.For accurate charge transfer,an operational ampliﬁer is used to force a virtual ground.For switched-capacitor stages,the ampliﬁer is required to have high input and output impedance,hence an operational transconductance ampliﬁer (OTA) is used.The accuracy of the virtual ground limits the accuracy

5 of the charge transfer since capacitor matching is high enough,especially in sub- micron processes.For the purposes of this thesis,the OTA will be represented by the symbol shown in Fig.2.1,and will be assumed to have inﬁnite bandwidth. 2.1.1 Sample-and-Hold Asample-and-hold (SAH) circuit is commonly used as a front-end of switched- capacitor ADCs.It relaxes the design requirement of the stages immediately suc- ceeding it.However,the accuracy of the SAH limits the accuracy of the ADC.A ﬂip-around SAH is shown in Fig.2.2.It consists of clocked switches,capacitors and an ampliﬁer.The two phase clock signals φ 1 and φ 2 are realized as non- overlapping phases.The input signal V S is sampled on the C f capacitors at the end of φ 1 .During φ 2 ,the capacitors are ﬂipped-around to feedback around the ampliﬁer.The next stage samples the output at the end of φ 2 .If the ampliﬁer is ideal,the capacitors maintain the charge sampled on them during φ 1 ,yielding an output voltage equal to the input.However,if the ampliﬁer has a ﬁnite DC gain, A,the diﬀerential output voltage becomes V O =

A 1 +A

V S =

1 − 1 1 +A

V S .(2.1) For high dynamic range,the ampliﬁer gain error and its nonlinearity has to be lower than the accuracy of the ADC.Another signiﬁcant design problem of the SAH is the noise requirement.The noise from the sampling switches and the ampliﬁer has to be below the quantization noise of the ADC.This requirement makes the SAH the most power consuming block in an ADC.

6

Figure 2.2:Flip-around sample-and-hold 2.1.2 Multiplying Digital-to-Analog Converter The multiplying digital-to-analog converter (MDAC) is a switched-capacitor block that acts as a digital-to-analog converter (DAC),a subtractor and a gain stage.The MDAC is most commonly used in residue-generating ADC structures, including sub-ranging,pipelined and algorithmic ADCs.A ﬂip-around realization of an MDAC is shown in Fig.2.3.As in the case of the SAH,the input signal is sampled on the capacitors at the end of φ 1 .One terminal of each capacitor is connected to the input of the ampliﬁer.The other terminal of the feedback capacitor C f is connected to the output of the MDAC while that of C s is connected to the DAC references during φ 2 .At the end of φ 2 ,the output of the MDAC, assuming an ideal ampliﬁer,can be expressed as V Oideal = C s +C f C f V S − C s C f D V R .(2.2)

7 Incorp orating the ﬁnite ampliﬁer gain results in an MDAC output that is less than the ideal output,and can be expressed as V O =

Aβ 1 +Aβ

V Oideal =

1 − 1 1 +Aβ

V Oideal .(2.3) where β is C f C s +C f and represents the feedback factor of the MDAC.The output error is inversely proportional to the loop gain of the MDAC,and has to be low enough to meet the accuracy requirement of the next MDAC stage.

Figure 2.3:Flip-around multiplying digital-to-analog converter 2.1.3 Integrator The integrator is used in switched-capacitor blocks with memory,like ﬁlters. It is commonly used in the loop ﬁlter of delta-sigma modulators.Fig.2.4 shows the schematic of a switched-capacitor integrator where the same capacitor is used for both the input sampling and the DAC references.The input signal is sampled on C s at the end of φ 1 .The charge on C s is then transferred to the integrating

8 capacitor C f during φ 2 .At the end of the charge transfer,the output of the integrator,assuming ideal ampliﬁer,can be expressed as V O = C s C f z −1 1 −z −1 [V S −D V R ].(2.4) The ﬁnite ampliﬁer gain adds a magnitude and phase error to the integrator output, yielding V O = C s C f

1 − 1 1 +Aβ

z −1 1 −[1 − 1−β 1+Aβ ]z −1 [V S −D V R ].(2.5)

Figure 2.4:Integrator with shared input and DAC capacitor The phase error determines the low frequency magnitude of the integrator transfer function.Ideally,the integrator transfer function approaches inﬁnity at DC.This property makes the integrator the block of choice for applications where suppression of slow moving signals is desired.In such applications,the lower the phase error,the better the low frequency suppression.

9 2.2 ADC Architectures Ampliﬁer ﬁnite gain deteriorates the performance of switched-capacitor cir- cuits,and for that matter switched-capacitor ADC.While high ampliﬁer gain is desirable,it comes with the cost of high power consumption.Understanding how ﬁnite ampliﬁer gain error aﬀects an ADC performance could therefore be helpful in deﬁning the minimum gain required for a given accuracy. 2.2.1 Flash ADC The ﬂash is the simplest analog to digital converter structure.In this ADC, an input signal is connected to a set of comparators.Each comparator is also con- nected to a diﬀerent threshold voltage.For the ﬂash ADC in Fig.2.5,the threshold voltages are determined by a resistor string.The outputs of the comparators give a digital representation of the analog input signal. The comparator thresholds are designed such that the outputs of the com- parator give a thermometer code representation of the signal.For the three- comparator ﬂash ADC of Fig.2.5,the threshold voltages are ( −V REF 2 ,0, V R EF 2 ). The possible set of comparator outputs are 000,001,011 and 111 depending on the region the input voltage falls.This output can then be decoded to a 2-bit word representation of the input signal.The ADC digital output can be written as D out · V REF = V IN + V REF 2 2 .(2.6) The second term on the right-hand side of Eq.(2.6) is the quantization error of the 2-bit ﬂash.For higher resolution,the number of bits used to represent the signal has to be increased.This results in lower quantization error.For an N-bit

10

Figure 2.5:2-bit ﬂash ADC ﬂash,the digital output becomes D OUT · V REF = V IN + V REF 2 N .(2.7) While the quantization error is signiﬁcantly reduced with higher number of bits,the number of comparators required to digitize the input signal increases exponentially.For instance,a 3-bit ﬂash requires 7 comparators while a 4-bit one requires 15 comparators.The number of comparators required for an N-bit ﬂash ADC is 2 N -1.The large number of comparators required for higher resolution ﬂash ADCs makes them power- and area-ineﬃcient.However,they can operate at very high conversion speeds since all the comparators are strobed at the same time.For high resolution,other ADC architectures are used.

11 2.2.2 Two-step ADC A more power- and area-eﬃcient way of increasing the resolution of ﬂash ADC,is to break the conversion into two separate steps.The number of bits resolved in each step is low so the number of comparator used is small.A block diagram of a two-step ADC is shown in Fig.2.6,where delays are omitted for clarity.The input signal is fed to the ﬁrst ﬂash ADC,which digitizes it with quantization error E 1 .This error is extracted by and MDAC and is digitized by the ﬂash ADC with an error E 2 .The ﬁnal output of the two-step ADC is obtained by summing the weighted digital outputs of the two ﬂash ADCs.For the ADC of

Figure 2.6:Two-step ADC Fig.2.6,the digital out is D OUT · V REF = D 1 + D 2 G .(2.8) D O UT · V REF = V IN +E 1 + 1 G (−G A E 1 +E 2 ).(2.9) D O UT · V REF = V IN +

1 − G A G

E 1 + 1 G E 2 .(2.10) If the closed loop gain of the MDAC (G A ) matches the digital gain (G),the quantization error from the ﬁrst stage of the ADC is completely canceled.The

12 remaining noise will be solely from the quantization error of the second stage, which is suppressed by the interstage gain.While it is easy to realize accurate digital gain,accurate analog gain is diﬃcult to achieve due to ﬁnite ampliﬁer gain. Using the MDAC gain expression derived from Eq.(2.3) and Eq.(2.10),the ADC output can be rewritten as D OUT · V REF = V IN + E 1 1 +Aβ + 1 G E 2 .(2.11) D O UT · V REF1 = V IN + 1 1 +Aβ V REF1 2 N1 + 1 G V R EF2 V R EF1 2 N2 .(2.12) Equation (2.12) deﬁnes the ampliﬁer gain requirement for a two-step ADC with a resolution of N 1 +N 2 bits.The matching between the references for the two stages could pose a problem since any mismatch will add to the gain error in the second term on the RHS of Eq.(2.12).To avoid this matching constraint,the MDAC could be designed such that G A =2 N1 .This allows the use of the same reference voltage for two subADCs.For example,a two-step ADC with a 4-bit ﬂash subADC will require an MDAC gain of 16 to use the same reference in both stages. 2.2.3 Pipelined ADC The pipelined ADC is a multiple stage extension of the two-step ADC.It has several stages that resolve only a few bits each.The sampling speed of the ADC is limited by the speed of just one stage,making the throughput of pipelined ADC very high.The latency associated with the pipelined conversion is not a problem in most applications,so a large number of stages could be used.Moreover,the small number of bits per stage results in an ADC with small area and low power operation.A block diagram of an n-stage pipelined ADC is shown in Fig.2.7.It consists of n-1 MDAC stages with a ﬂash subADC at the end.

13

Figure 2.7:Pipelined ADC The digital output of the ADC is the weighted sum of all the outputs of the subADCs after taking care of the latency.The output can be written as D OUT · V REF = D 1 + D 2 G 1 + D 3 G 1 G 2 + D n G 1 G 2 G 3 ...G n .(2.13) D O UT ·V REF = V IN +

1− G A1 G 1

E 1 +

1− G A2 G 2

E 2 +...+ 1 G 1 G 2 G 3 ...G n−1 E n .(2.14) If G Ai = G i ,the ADC output reduces to D OUT · V REF = V IN + 1 G 1 G 2 G 3 ...G n−1 E n = V I N + 1 G 1 G 2 G 3 ...G n−1 V R EF 2 N n .(2.15) Equation (2.15) indicates that the accuracy of the pipelined ADC depends on the resolution of the back-end ﬂash ADC and the product of the gains of the stages.Finite ampliﬁer gain causes the quantization noise of the earlier stages to leak through to the output.The digital output of the pipelined ADC with a non-ideal ampliﬁer gain is D OUT ·V REF = V IN + 1 (1 +Aβ) 1 E 1 + 1 G 1 1 (1 +Aβ) 2 E 2 +...+ 1 G 1 G 2 ...G n−1 E n .(2.16)

14 Equation (2.16) gives the eﬀect each MDAC gain error has on the entire ADC performance.The loop gain requirement gets relaxed down the pipeline since the accuracy requirement tapers down the pipeline too.It might seem from the above expression that a straightforward way of reducing the loop gain requirement is to resolve more bits in the ﬁrst stage.However,the higher the number of bits resolved, the higher the required MDAC gain,which implies lower feedback factor.Thus, the reduction in the loop gain requirement is oﬀset by the reduction in feedback factor,leaving the ampliﬁer gain requirement unchanged. One important consideration in designing pipelined ADCs is the oﬀset in the subADCs.If the subADC oﬀset is too high,the residue voltage will exceed the range of the next subADC leading to lost information.If the MDAC gain is chosen to be 2 M−1 instead of 2 M for an M-bit stage,the eﬀect of the subADC oﬀset and nonlinearity is reduced [5].However,this reduces the eﬀective number of bits per stage and hence requires more stages to resolve a given number of bits.The redundancy does not complicate the digital output summation or,as it popularly called,digital error correction. The transfer curve of a 10-bit pipelined ADC is shown in Fig.2.8.The pipeline has four stages resolving 2.5 eﬀective bits each and a 2-bit ﬂash in the back-end.The 2.5bit stage has six comparators in the subADC (7 levels) and an MDAC with a gain of 4.A 20-dB loop gain is used in the ﬁrst MDAC while the remaining stages remain ideal.As is evident from the Fig.2.8,the gain error causes vertical jumps in the ADC transfer curve when the input transitions from one region of the subADC to another.This will cause nonlinearities in the ADC spectrum and degrade signal to noise and distortion ratio (SNDR). Another way of decreasing the quantization noise in a pipelined ADC is to oversample the input signal.The quantization noise of the pipelined ADC is spread

15 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 Analog Input [V] Digital Output [V]

Actual ADC Ideal ADC Figure 2.8:Eﬀect of gain error in pipelined ADC linearity evenly in the Nyquist band due to aliasing.If the signal bandwidth is less than Nyquist,the amount of quantization noise in the signal band is reduced.The signal to quantization noise ratio (SQNR) of the ADC increases by 3dB for every doubling of the oversampling ratio. 2.2.4 Delta-Sigma ADC The delta-sigma ADC improves on the idea of oversampling to realize high accuracy ADCs.A loop ﬁlter is used to suppress the inband quantization noise of the delta-sigma modulator.While the oversampling and noise shaping are instru- mental in the achieving high accuracy,the signal bandwidth is limited to a few MHz especially for resolutions beyond 12bits.The loop ﬁlter that determines the noise shaping could be either lowpass (quantization noise is high-pass ﬁltered) or bandpass (quantization noise is notch ﬁltered),and could be of any order.

16 The block diagram of a lowpass delta-sigma modulator is shown in Fig.2.9. A 2nd order low-distortion topology [6] is used in this example.There are two full delay integrators in the loop,and parameters δ and α in their transfer functions are ideally unity.

Figure 2.9:Delta-sigma ADC The signal transfer function (STF) from V IN to D OUT and the noise transfer function (NTF) from E to D OUT can be written as STF = 1 +2I +I 2 1 +2I +I 2 = 1.(2.17) NTF = 1 1 +2I +I 2 = (1 −αz −1 ) 2 1 −2(α −δ)z −1 + (α 2 −2αδ +δ 2 )z −2 .(2.18) where the integrator transfer functions are assumed to be identical and represented by I.If the magnitude and phase errors are zero,the NTF reduces to a 2nd order highpass ﬁlter with both of its zeroes at DC,as shown in Eq.(2.19) NTF = (1 −z −1 ) 2 .(2.19) However,in the presence of ﬁnite ampliﬁer gain,the NTF becomes NTF =

1 −

1 − 1−β 1+Aβ

z −1

2

1 − β 1+Aβ z −1

2 .(2.20)

17 This limits the low frequency attenuation of the loop and degrades inband quanti- zation noise suppression.From Eq.(2.20),the magnitude of the NTF at DC can be derived as NTF(z = 1) = 1 [1 +A] 2 .(2.21) For an ampliﬁer with a 40-dB gain,the attenuation of the NTF at DC is 80-dB. This is illustrated in Fig.2.10.For higher suppression,the ampliﬁer gain has to be increased accordingly. 10 −4 10 −3 10 −2 10 −1 10 0 −160 −140 −120 −100 −80 −60 −40 −20 0 20 Normalized Frequency [ ω / π ] Magnitude [dB]