• unlimited access with print and download
    $ 37 00
  • read full document, no print or download, expires after 72 hours
    $ 4 99
More info
Unlimited access including download and printing, plus availability for reading and annotating in your in your Udini library.
  • Access to this article in your Udini library for 72 hours from purchase.
  • The article will not be available for download or print.
  • Upgrade to the full version of this document at a reduced price.
  • Your trial access payment is credited when purchasing the full version.
Buy
Continue searching

Integrated Circuits and Systems for Sparse Signal Acquisition based on Asynchronous Sampling and Compressed Sensing

ProQuest Dissertations and Theses, 2011
Dissertation
Author: Michael Trakimas
Abstract:
This dissertation builds on the recent theoretical and experimental work on asynchronous sampling and compressed sensing. Our goal is to exploit the advances in the theory to design practical data acquisition systems capable of directly acquiring sparse signals at sub-Nyquist rates. We focus specifically on increasing the power efficiency and decreasing the complexity of the signal acquisition process compared to existing conventional Nyquist rate solutions for biomedical sensor and wideband spectrum sensing applications. The first half of the dissertation presents the design and implementation of an adaptive resolution asynchronous ADC which achieves data compression for sparse and burst like signals by the inherent signal dependent sampling rate of the asynchronous architecture. The main contribution of this work is the implementation of an adaptive resolution (AR) algorithm which varies the quantizer resolution of the ADC with the slope of the input signal, in order to overcome the tradeoff between dynamic range and input bandwidth typically seen in asynchronous ADCs. This allows the maximum possible input bandwidth to be achieved regardless of the dynamic range requirement. By reducing the quantizer resolution during periods of high input slope, further data compression is also achieved. A prototype ADC was fabricated in a 0.18µm CMOS technology and optimized for subthreshold operation in order to increase the power efficiency for low-frequency biomedical sensor applications. The prototype ADC achieves an equivalent maximum sampling rate of 50kS/s, an SNDR of 43.2dB, and consumes 25µW from a 0.7V supply. The ADC is also shown to provide data compression for accelerometer and ECG applications as a proof of concept demonstration. The second half of this dissertation presents the design and implementation of a compressed sensing based analog-to-information converter (AIC) for wideband spectrum sensing applications. The core of the design is an ultra low power moderate rate ADC that randomly samples the received signal at sub-Nyquist rates. In order to ensure proper functionality with the random clock signal and to maximize power efficiency, a prototype edge-triggered charge-sharing SAR ADC core was implemented in 90nm CMOS technology. The prototype SAR ADC core achieves a maximum sample rate of 9.5MS/s, an ENOB of 9.3 bits, and consumes 550µW from a 1.2V supply. Measurement results of the compressed sensing AIC demonstrate effective sub-Nyquist random sampling and reconstruction of signals with sparse frequency support suitable for wideband spectrum sensing applications. When accounting for the increased input bandwidth compared to Nyquist, the AIC achieves an effective figure of merit (FOM) of 10.2fJ/conversion-step.

Table of Contents List of Figures viii List of Tables xv Acknowledgements xvi 1 Introduction 1 1.1 Research Motivation ............................................................................. 1 1.2 Summary ............................................................................................... 6 2 Nyquist Rate Data Acquisition 11 2.1 Analog-to-Digital Conversion .............................................................. 12 2.1.1 Resolution ................................................................................. 13 2.1.2 Sampling Rate .......................................................................... 15 2.2 ADC Architectures ............................................................................... 17 2.3 Data Compression ................................................................................ 19 3 Asynchronous Sampling 29 3.1 Introduction .......................................................................................... 29 3.2 Background Theory .............................................................................. 35 3.2.1 Signal-to-Noise Ratio ............................................................... 36 3.2.2 Maximum Sampling Rate ......................................................... 38 3.2.3 Input Bandwidth ....................................................................... 38

v

3.2.4 Dynamic Range 39 4 Adaptive Resolution Asynchronous ADC 40 4.1 Introduction .......................................................................................... 40 4.2 Input Bandwidth/Dynamic Range Tradeoff ......................................... 43 4.3 Adaptive Resolution Algorithm ........................................................... 46 4.4 ADC Architecture ................................................................................. 47 4.4.1 ADC Operation ......................................................................... 47 4.4.2 Resolution Controller ............................................................... 50 4.5 Circuit Design ....................................................................................... 56 4.5.1 DAC .......................................................................................... 56 4.5.2 Operational Transconductance Amplifier ................................ 59 4.5.3 Comparator and Offset Calibration .......................................... 62 4.5.4 Control Logic and Timer .......................................................... 66 4.6 Measured Results .................................................................................. 67 4.6.1 ADC Performance with AR Algorithm .................................... 69 4.6.2 Comparison to Fixed Quantizer Resolution ............................. 73 4.6.3 Accelerometer Test ................................................................... 78 4.6.4 ECG Test .................................................................................. 80 4.7 Chapter Summary ................................................................................. 81 5 Compressed Sensing 85 5.1 Introduction .......................................................................................... 85 5.2 Background Theory .............................................................................. 88 5.2.1 Sparse Signals ........................................................................... 88

vi

5.2.2 Compressed Measurements ...................................................... 89 5.2.3 Signal Recovery ........................................................................ 92 6 Random Sampling Analog-to-Information Converter 94 6.1 Introduction .......................................................................................... 94 6.2 Random Sampling AIC Architecture ................................................... 99 6.3 Edge-Triggered Charge-Sharing SAR ADC ........................................ 101 6.3.1 Architecture .............................................................................. 101 6.3.2 Circuit Design ........................................................................... 105 6.3.2.1 DAC ........................................................................... 105 6.3.2.2 Comparator ................................................................. 106 6.3.2.3 Sample-and-Hold ....................................................... 109 6.3.2.4 Asynchronous Controller ........................................... 111 6.4 Measured Results .................................................................................. 113 6.4.1 SAR ADC ................................................................................. 113 6.4.2 Compressed Sensing AIC ......................................................... 118 6.4.3 Reconstruction Performance with Basis Mismatch .................. 122 6.4.4 Figure of Merit ......................................................................... 125 6.5 Chapter Summary ................................................................................. 125 7 Conclusions and Future Research 127 A Test Setups 131 A.1 Asynchronous ADC .............................................................................. 131 A.2 SAR ADC ............................................................................................. 133 A.3 Compressed Sensing AIC ..................................................................... 134

vii

Bibliography 136

viii

List of Figures 1.1 Wireless body area network with typical wireless sensor block diagram Compressed Sensing AIC ................................ ..................... 4 2.1 Digital signal acquisition system ......................................................... 12 2.2 Simplified ADC block diagram ........................................................... 13 2.3 (a) Input-output transfer curve for 3-bit quantizer. (b) Quantization error versus normalized input amplitude ................................ ............. 14 2.4 Probability density function of quantization noise .............................. 15 2.5 Example sampling operation of an analog signal bandlimited to a maximum frequency of f 0 . (a) Input signal and spectrum. (b) Sampled signal and spectrum when fs > 2f 0 . (c) Sampled signal and spectrum when Nyquist criterion is not satisfied

................................ 16 2.6 Successive approximation register ADC architecture ......................... 18 2.7 Successive approximation conversion ................................................ 19 2.8 Successive approximation algorithm .................................................. 20 2.9 Scaling and wavelet functions for Daubechies-4 wavelet ................... 23 2.10 Filter bank implementation of wavelet decomposition ....................... 24 2.11 Example of wavelet based image compression. (a) Original image. (b) 4 -level Daubechies- 4 wavelet decomposition. (c) Reconstructed 26

ix

image from 10% of decomposition coefficients. (d) Residual image. 2.12 Example of wavelet based image compression. (a) Original image. (b) 4 -level Daubechies- 4 wavelet decomposition. (c) Reconstructed image from 10% of decomposition coefficients. (d) Residual image. 27 2.13 Example of wavelet based compression of an ECG signal. (a) Original signal, reconstructed signal from 10% of wavelet decomposition coefficients, and residual signal. (b) 4-level Daubechies -4 wavelet decomposition ................................ ................. 28 3.1 Non-uniform sampling of a signal by an asynchronous ADC. The samples are shown as dots ................................ ................................... 30 3.2 (a) Example input and demodulated output waveforms for an asynchronous delta - modulation system. (b) Corresponding delta modulated waveform ................................................................ ........... 31 3.3 Example architecture of a flash based level crossing ADC ................ 32 3.4 Block diagram of an asynchronous sigma-delta ADC architecture .... 33 3.5 (a) Delay line time-to-digital converter. (b) Vernier delay line time- to- digital converter ................................................................ .............. 34 3.6 Error due to quantization of time in asynchronous sampling .............. 37 4.1 Example waveforms of a signal asynchronously sampled with the quantizer resolution: (a) set to the maximum value that meets the input bandwidth requirement of the signal; (b) set to the minimum value that meets the dynamic range requirement of the signal; (c) varied with the input slope, allowing both the input bandwidth and 44

x

dynamic range requirements of the signal to be met ........................... 4.2 (a) Architecture of the proposed AR asynchronous ADC. (b) Example waveforms demonstrating operation of proposed ADC. (c) Simplified block diagram of the resolution controller

........................ 48 4.3 Simplified flowchart of the AR algorithm. RES is the quantizer resolution and Δt

is the time since the previous threshold crossing... 52 4.4 Simulated response of the ADC for different values of the Δt thresholds used to control the AR algorithm. (a) Response to a step function filtered at the bandwidth of the ADC, for different values of the lower Δt threshold. (b) Response to a sinusoidal inp ut with frequency equal to the bandwidth of the ADC, and amplitude which drops from full - scale to the minimum value within the dynamic range of the ADC, for different values of the upper Δt threshold ....... 54 4.5 10-bit fully-differential hybrid switch-capacitor/resistor-string DAC and example timing waveform. For clarity, only one side is shown.. 57 4.6 (a) Two-stage Miller-compensated OTA. (b) Common-mode feedback circuit ................................................................ ................... 60 4.7 OTA simulated open-loop frequency response ................................... 62 4.8 Continuous-time Comparator .............................................................. 63 4.9 Simulated input dependent decision delay of the continuous-time comparator ................................................................ ........................... 64 4.10 Simulated SNDR versus the difference in comparator offset for a 34Hz sinusoidal input with amplitude of 535mV, a timer resolution 65

xi

of 1MHz, a loop-delay of 20μs, and a quantizer resolution of 8 bits. 4.11 Die micrograph of the prototype ADC ................................................ 68 4.12 ADC output spectrum for a 1.1kHz sinusoidal differential input with amplitude of 570mV. A 6 th - order polynomial interpolator was used to reconstruct a synchronous signal at 20kS/s from the sampled output, so that standard FFT techniques could be used to compute the output spectrum. Even order distortion is due to some of the ESD diodes in the prototype chip being connected to the wrong supply. SNDR and ENOB values are given both not including* and including this distortion ................................ .............. 70 4.13 Comparison of SNDR versus input amplitude for when the quantizer resolution was set by the AR algorithm and fixed at 4, 6, and 8 bits. The SNDR was calculated for a 40Hz sinusoidal differential input ................................................................ .................. 74 4.14 Comparison of SNDR versus input frequency for when the quantizer resolution was set by the AR algorithm and fixed at 4, 6, and 8 bits. The SNDR was calculated for a sinusoidal differential input with amplitude of 570mV ................................ .......................... 75 4.15 Comparison of input bandwidth versus dynamic range, calculated from Fig. 4.13 and 4.14 , for when the quantizer resolution was set by the AR algorithm and fixed at 4, 6, and 8 bits

............................... 76 4.16 Sampled output of the ADXL335 accelerometer and corresponding time varying sample ra te ................................ ..................................... 79

xii

4.17 Measured ECG signal at ADC output and corresponding time varying sample rate ................................................................ ............. 81 5.1 Conventional direct sampling architecture for distributed wideband spectrum sensing application ................................ .............................. 86 5.2 Sparse representation of input signal x with K = 4 .............................. 89 5.3 (a) Compressed sensing measurement process. The length N vector of coefficients α is sparse with K = 4. (b) The measurement vector y is a linear combination of K columns from matrix ΦΨ ....................... 90 6.1 Block diagram of the random demodulator ......................................... 95 6.2 Block diagram of the modulated wideband converter......................... 96 6.3 Block diagram of CS wireless bio-sensor ........................................... 97 6.4 Block diagram of proposed compressed sensing AIC based acquisition system ................................................................ ............... 100 6.5 Schematic of pseudo-random clock generator. Restricting the minimum sample spacing relaxes the requirements of the ADC ........ 101 6.6 Architecture of the proposed edge-triggered charge-sharing SAR ADC ................................................................ .................................... 102 6.7 (a) Simplified schematic of the sample-and-hold capacitors and DAC during the conversion. (b) Example control signal waveforms for the first 2 bits of the conversion ................................ .................... 104 6.8 (a) Schematic of the DAC. (b) Example control signal waveform during precharging ................................................................ .............. 106 6.9 Two-stage dynamic latched comparator ............................................. 107

xiii

6.10 Comparator input-referred noise and comparison time versus common -mode input voltage ................................ ............................... 108 6.11 (a) Sample-hold circuit. (b) Bootstrap nMOS sampling switch .......... 110 6.12 500ps unit delay cell ............................................................................ 112 6.13 Die micrograph of the SAR ADC ....................................................... 113 6.14 Measured INL and DNL at V DD = 1.2V and F S = 9.5MS/s................. 115 6.15 Measured ADC output spectrum at 1.2V and FS = 9.5MS/s for a full -scale (a) 100kHz and (b) near Nyquist input ................................ 116 6.16 Measured ENOB versus input frequency at V DD = 1.2V, F S = 9.5MS/s, and A IN = -0.5dBFS ................................ ............................. 117 6.17 Full-power bandwidth measurements ................................................. 117 6.18 Measured ENOB, normalized to a full-scale input, versus input frequency at V DD = 1.2V and F S = 9.5MS/s ........................................ 118 6.19 Example signals from demonstration of proposed compressed sensing ADC based acquisition system. (a) Input signal and spectrum. (b) Reconstructed signal and spectrum from MATLAB simulations. (c) Reconstructed signal and spectrum from measurements ................................................................ ...................... 120 6.20 (a) Average reconstructed SNDR and (b) frequency support recovery rate versus signal sparsity (K), for varying input SNR ........ 121 6.21 Average reconstructed SNDR versus signal sparsity, for varying (a) input bandwidth and (b) N ................................ .................................. 123 6.22 Average reconstructed SNDR versus normalized frequency 124

xiv

mismatch, with and without sampled data multiplied by a window function ................................................................ ................................ A.1 Test setup for asynchronous ADC FFT tests ...................................... 132 A.2 Test setup for asynchronous ADC accelerometer test ........................ 132 A.3 Test setup for SAR ADC performance measurements ........................ 134 A.4 Test setup for compressed sensing AIC performance measurements. 135

xv

List of Tables 2.1 Overview of different ADC architectures ........................................... 17 4.1 OTA component sizes ......................................................................... 61 4.2 Comparator component sizes .............................................................. 63 4.3 ADC performance summary ............................................................... 72 6.1 Comparator component sizes .............................................................. 108 6.2 Bootstrap switch component sizes ...................................................... 111 6.3 Delay line unit cell component sizes ................................................... 111 6.4 ADC performance summary ............................................................... 114

xvi

Acknowledgements I would first like to thank my adviser, Professor Sameer Sonkusale, for all the support he has given me throughout my time at Tufts University. I am especially grateful for the freedom he has allowed me in defining and pursuing research which interests me. It has been a great experience working in his research group, the NanoLab, and seeing how it has grown from its formation a year before I joined. I would also like to thank the members of my dissertation defense committee, Professor Hwa Chang, Professor Valencia Joyner, and Dr. Timothy Hancock for their interest, time, and feedback given to my dissertation. I would like to thank Professor Chang, who was my undergraduate adviser, for always showing interest in my development as both a student and a person throughout both my undergraduate and graduate years at Tufts University. I have enjoyed working with all the other members of the NanoLab over the past several years, especially the group of students who all joined around the same time as I did, which includes Sungkil Hwang, Jon Chow, Krenar Komoni, Ashwin Duggal, Vinay Agarwal, Ritika Agarwal, Jian Guo, Kyoungchul Park, Sam MacNaughton, Saroj Rout, and Wangren Xu. I am thankful for the help they have provided me with my research as well as the friendship and common experiences we have shared over the past several years.

xvii

This work would not have been possible without the support I received from MIT Lincoln Laboratory over the past several years. I am grateful for not only the financial support they have provided me to pursue my research, but also for providing me with an office at the laboratory so that I could take advantage of their many resources as well as interact with the staff. I would especially like to thank Tim Hancock, who served as my supervisor at the laboratory, for always taking the time to help me with any problem I have had with my research or to just listen to me complain for the last year about wanting to graduate. His help has been invaluable and greatly improved the quality of my work as well as forwarded my development as a professional engineer. I would also like to thank Mark Gouker and Leonard Johnson for bringing me in as a member of Group 86, as well as all the other members of our group for their help and support over the past several years. While there are too many people at the laboratory to mention them all, I would especially like to thank my officemates Jeff Myer, Chris Galbraith, and Mike Hamilton for their support and technical insight as I have been finishing up my dissertation this past year, as well as Milan Raj and Brian Tyrrell for their help with chip fabrication. Finally, I would like to thank my parents and sisters, Nicole and Danielle, for all the support and love they have given me not only during my graduate years but throughout my life. This work would have not been possible without all the opportunities they have provided me in life. Last, but of course not least, I want to thank my girlfriend Christine. I’m sure when we met a week before I entered graduate school she had no idea what she was getting into. Thank you for all of

xviii

the constant support, patience, and love you have given me throughout these past six years. I look forward to our future together, which I promise will include no more practice runs of my defense talk.

1

Chapter 1 Introduction 1.1 Research Motivation

Throughout human history, we have always strived to acquire as much information as possible from the world around us. Arguably the greatest impact on our ability to acquire and interpret information from the world we live in has been the advent of modern electronics. This has allowed us to use specially designed sensors to acquire real world signals in electronic form, and then use electronic signal processing to extract, store, and transmit the information embedded in them. Traditionally, most signal processing was done in the analog domain, which limited the processing capabilities available to us. A shift began with the pioneering work done by Whittaker, Nyquist, Kotel’nikov, and Shannon [1]-[4], which demonstrated that bandlimited, continuous time signals, can be exactly recovered from a set of uniformly-spaced samples taken at the Nyquist rate of twice the bandlimit. This allowed signal processing to move from the analog to the digital domain. When combined with the ever increasing processing power provided by Moore’s law [5], this has allowed for the creation of more complex

2

sensing and processing systems which are more robust, flexible, and cheaper than their analog counterparts. While sensing technology greatly benefited from the move to digital signal processing, it was not until recent advances in wireless communication technology when its full potential would be realized. This has become evident in our everyday life where wireless sensors are now embedded in everything from the phones we carry to the cars we drive. Other examples of the diverse tasks now performed by wireless sensing systems are the monitoring of our health, providing wide area constant surveillance in both civilian and military applications, and acquiring environmental data in environments which are inhospitable to humans, among countless others tasks. While wireless communication technology has expanded the range of potential applications for sensing technology, the fact that each sensor must now operate from a battery or other energy limited supply has its own set of challenges. This is exacerbated in emerging technologies such as biomedical implants where the battery size is severely constrained and replacing the battery is inconvenient. Therefore, it is desirable to design each sensor with as low complexity and power consumption as possible, in order to increase their operational lifetime as well as decrease their size, weight, and cost. In many applications this is accomplished by offloading as much of the signal processing and analysis as possible to a central processing node or other external device. Each sensor is then tasked with acquiring the signals of interest, storing them, and

3

eventually transmitting them back to the central processing node, where ample power and processing resources are available. In order to reduce the transmission and storage requirements of each sensor, digital compression algorithms are often employed to compress the data once it has been acquired. Conventional compression techniques operate on the full Nyquist rate signal by first transforming the signal into a domain where it has a sparse representation and then encoding only a certain number of the largest transform coefficients. For signals which are sparse or compressible, the majority of the coefficients can be discarded with minimal loss of information. While this “acquire-then-compress” technique improves the transmission power efficiency of the sensor and reduces the memory requirements, it actually increases the complexity and power consumption of the signal acquisition process due to the additional compression algorithms needed. For emerging technologies such as wireless body area networks (WBANs) [6]-[9] and cognitive radio [10]-[13], a more efficient signal acquisition process is desirable. Recent interest in WBANs has been driven by the desire for low-cost continuous ambulatory monitoring of patients with chronic diseases, those recovering from surgery, etc. For example, continuous monitoring of a patient’s blood pressure in their natural environment allows for a more accurate diagnosis compared to relying on a one time measurement at the doctor’s office. Long term electrocardiogram (ECG) monitoring could also be used to detect an impending heart attack for at risk patients. Figure 1.1 illustrates a simple representation of an example WBAN, where wireless sensors are used to sense and acquire various

4

vital signs and transmit them to a central processing node, which could be a smart phone or PDA. The acquired information could then be displayed to the patient or transmitted to a physician to allow timely and more accurate diagnosis and response to emergency situations. Typical sensors may include ECG and electroencephalography (EEG) electrodes, accelerometers, blood pressure and glucose monitors, pulse oximeters, etc. A block diagram of a typical sensor node is shown in Fig. 1.1, and will be described in more detail in the next chapter. Since each sensor will be worn on the patient’s body or implanted inside of them, it is critical that they be as unobtrusive and low maintenance as possible. This is especially true for implantable devices, for which replacement of the power source is particularly concerning. If the power consumption of each sensor node can be reduced to 10s of μWs or less, then energy scavenging could be used to allow autonomous operation for the required lifetime of the implant [14]-[17]. In light of the extreme energy and size constraints placed on each sensor in WBAN applications, the increased complexity and power consumption of the “acquire-then-compress” signal acquisition process described previously is

Figure 1.1:

Wireless body area network with typical wireless sensor block diagram.

Sensor Signal Conditioning ADC DSP/ Memory ...101101010… ECG Accelerometer Blood Pressure Pulse Oximeter Tx

5

undesirable. A more efficient signal acquisition process could be designed if the signal could be directly acquired in compressed form without the need for additional compression algorithms. This has been the focus of recent work on asynchronous sampling [18]-[26] and compressed sensing [27]-[35]. Asynchronous sampling is an event driven signal acquisition approach which exploits the sparsity in time of certain types of signals such as those often seen in ECG and EEG monitoring applications, hearing aids, implantable biomedical diagnostic devices, and certain environmental sensors. By only sampling the input signal when it changes by a preset amount, burst-like or sparsely active signals can be directly acquired at sub-Nyquist rates and later reconstructed with close to full fidelity. Similarly, compressed sensing exploits a priori knowledge that a signal is sparse or compressible in some basis to design a measurement process which directly acquires the signal at sub-Nyquist rates. Both of these techniques effectively trade reconstruction efficiency for a reduction in sample rate. This is advantageous for energy constrained wireless sensor applications where signal analysis is performed remotely at a central processing node or other device with ample power and processing resources. Compressed sensing also has the potential to improve the signal acquisition process in the emerging field of cognitive radio. First presented by Mitola in [13], cognitive radio is a paradigm for wireless communication in which each wireless node adapts its transmission and reception frequency depending on the spectrum occupancy in its area. This allows for a more efficient usage of increasingly scarce spectrum real estate by allowing unlicensed secondary users to access a

6

band licensed to primary users when it is unoccupied. Wideband spectrum sensing [36]-[38] plays an important role in cognitive radio since the secondary user must continuously monitor the full spectrum to avoid transmitting in a band occupied by a primary user. This is also an essential function in signal intelligence applications where the RF spectrum in different areas is monitored to determine the frequency of emitters, among other tasks. Conventional Nyquist rate solutions for wideband spectrum sensing often employ either a bank of tunable narrowband band-pass filters which scan across the frequency band of interest, or a high speed ADC to directly acquire the full spectrum [39]. The increased complexity of the filter bank approach and very high sampling rates required by the direct sampling approach make it difficult to design low cost and power efficient wideband spectrum sensing systems. This is especially troubling for autonomous wireless sensor applications where replacing the battery is difficult or may not be possible at all. Since the RF spectrum to be monitored is often sparse in the frequency domain, compressed sensing can instead be used to directly acquire the entire spectrum in compressed form at sub- Nyquist rates. This would reduce the complexity and power consumption of the signal acquisition process and relax the requirements of the ADC, leading to increased operational lifetime and decreased cost for each sensor. 1.2 Summary

This dissertation builds on the recent theoretical and experimental work on asynchronous sampling and compressed sensing. Our goal is to exploit the

7

advances in the theory to design practical data acquisition systems capable of directly acquiring sparse signals at sub-Nyquist rates. We focus specifically on increasing the power efficiency and decreasing the complexity of the signal acquisition process compared to existing conventional Nyquist rate solutions for biomedical sensor and wideband spectrum sensing applications. We assume that in our applications of interest, the signal will be reconstructed and analyzed remotely where ample power and processing resources are available. In this spirit, the first half of this dissertation presents the design and implementation of an asynchronous analog-to-digital converter (ADC) targeted at biomedical signal acquisition applications such as ECG and EEG monitoring. The ADC was fabricated in a 0.18μm CMOS process and optimized for subthreshold operation in order to increase the power efficiency for low-frequency biomedical sensor applications. The main contribution of this work was the implementation of an adaptive resolution algorithm which varied the quantizer resolution of the ADC with the slope of the input signal, in order to overcome the tradeoff between dynamic range and input bandwidth typically seen in asynchronous ADCs. This allowed the maximum possible input bandwidth to be achieved regardless of the dynamic range requirement. By reducing the quantizer resolution during periods of high input slope, further data compression was also achieved. The second half of this dissertation presents the design and implementation of a compressed sensing based analog-to-information converter (AIC) for wideband spectrum sensing applications. The core of the design is an ultra low power moderate rate ADC that randomly samples the received signal at sub-Nyquist

8

rates. In order to ensure proper functionality with the random clock signal and to maximize power efficiency, a prototype edge-triggered charge-sharing SAR ADC was implemented in 90nm CMOS technology. Measurement results for wideband spectrum sensing demonstrate that our proposed compressed sensing AIC improves power efficiency and reduces complexity compared to the conventional direct sampling architecture, while still maintaining high performance for signals with sparse frequency support. We also analyze and propose solutions to issues which have not been fully addressed in previous works but arise in practice, such as mismatch between the chosen basis functions and the actual received signal. The main contribution of this work was the implementation of a physical compressed sensing acquisition system which moved beyond the proof-of-concept stage and improved power efficiency and reduced system complexity compared to existing solutions for wireless sparse spectrum sensing applications. This chapter has presented a brief overview of the evolution of electronic data acquisition systems and why it is important in modern wireless sensor applications such as WBANs and cognitive radio to improve the power efficiency and reduce the complexity of the signal acquisition process. We have also introduced asynchronous sampling and compressed sensing as two sub-Nyquist signal acquisition methods capable of achieving these goals. In the following chapter we give a more detailed overview of traditional Nyquist rate digital signal acquisition and give some examples of traditional data compression techniques used to reduce storage and transmission requirements. This serves to provide a

9

good foundation to compare our proposed asynchronous sampling and compressed sensing based signal acquisition systems to. In Chapter 3, we introduce the theory behind asynchronous sampling and discuss how it can be used to improve the power efficiency and reduce the complexity of the signal acquisition process for signals with sparse activity in time. In Chapter 4, we present the design and implementation of our proposed asynchronous ADC as well as our proposed adaptive resolution algorithm which overcomes the tradeoff between input bandwidth and dynamic range typically seen in asynchronous ADC designs. Measurement results comparing the performance of our proposed adaptive resolution ADC to asynchronous ADCs with fixed quantizer resolution are then presented followed by measured results demonstrating direct data compression for accelerometer and ECG applications. In Chapter 5, we give a brief overview of the theory behind compressed sensing and discuss how it can be used to improve the power efficiency and reduce the complexity of the signal acquisition process for signals which are sparse in some basis. In Chapter 6 we present the design and implementation of our proposed compressed sensing based AIC. The core of the design is an ultra low power edge-triggered charge-sharing SAR ADC that randomly samples the input signal at sub-Nyquist rates. Measurement results of the AIC demonstrate sub-Nyquist sampling and reconstruction of signals with sparse frequency support suitable for wideband spectrum sensing applications. The power efficiency and complexity of the proposed compressed sensing AIC based acquisition system is then compared with the conventional Nyquist rate sampling approach for

Full document contains 163 pages
Abstract: This dissertation builds on the recent theoretical and experimental work on asynchronous sampling and compressed sensing. Our goal is to exploit the advances in the theory to design practical data acquisition systems capable of directly acquiring sparse signals at sub-Nyquist rates. We focus specifically on increasing the power efficiency and decreasing the complexity of the signal acquisition process compared to existing conventional Nyquist rate solutions for biomedical sensor and wideband spectrum sensing applications. The first half of the dissertation presents the design and implementation of an adaptive resolution asynchronous ADC which achieves data compression for sparse and burst like signals by the inherent signal dependent sampling rate of the asynchronous architecture. The main contribution of this work is the implementation of an adaptive resolution (AR) algorithm which varies the quantizer resolution of the ADC with the slope of the input signal, in order to overcome the tradeoff between dynamic range and input bandwidth typically seen in asynchronous ADCs. This allows the maximum possible input bandwidth to be achieved regardless of the dynamic range requirement. By reducing the quantizer resolution during periods of high input slope, further data compression is also achieved. A prototype ADC was fabricated in a 0.18µm CMOS technology and optimized for subthreshold operation in order to increase the power efficiency for low-frequency biomedical sensor applications. The prototype ADC achieves an equivalent maximum sampling rate of 50kS/s, an SNDR of 43.2dB, and consumes 25µW from a 0.7V supply. The ADC is also shown to provide data compression for accelerometer and ECG applications as a proof of concept demonstration. The second half of this dissertation presents the design and implementation of a compressed sensing based analog-to-information converter (AIC) for wideband spectrum sensing applications. The core of the design is an ultra low power moderate rate ADC that randomly samples the received signal at sub-Nyquist rates. In order to ensure proper functionality with the random clock signal and to maximize power efficiency, a prototype edge-triggered charge-sharing SAR ADC core was implemented in 90nm CMOS technology. The prototype SAR ADC core achieves a maximum sample rate of 9.5MS/s, an ENOB of 9.3 bits, and consumes 550µW from a 1.2V supply. Measurement results of the compressed sensing AIC demonstrate effective sub-Nyquist random sampling and reconstruction of signals with sparse frequency support suitable for wideband spectrum sensing applications. When accounting for the increased input bandwidth compared to Nyquist, the AIC achieves an effective figure of merit (FOM) of 10.2fJ/conversion-step.