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Fully Differential Difference Amplifier based Microphone Interface Circuit and an Adaptive Signal to Noise Ratio Analog Front end for Dual Channel Digital Hearing Aids

ProQuest Dissertations and Theses, 2011
Dissertation
Author: Syed Roomi Naqvi
Abstract:
A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems (MEMS) microphones and an adaptive-power analog font end (AFE) is presented. The Microphone interface circuit based on FDDA converts the capacitance variations into voltage signal, achieves a noise of 32 dB SPL (sound pressure level) and an SNR of 72 dB, additionally it also performs single to differential conversion allowing for fully differential analog signal chain. The analog frontend consists of 40dB VGA and a power scalable continuous time sigma delta ADC, with 68dB SNR dissipating 67uW from a 1.2V supply. The ADC implements a self calibrating feedback DAC, for calibrating the 2 nd order non-linearity. The VGA and power scalable ADC is fabricated on 0.25 um CMOS TSMC process. The dual channels of the DHA are precisely matched and achieve about 0.5dB gain mismatch, resulting in greater than 5dB directivity index. This will enable a highly integrated and low power DHA.

v TABLE OF CONTENTS Page

LIST OF TABLES .......................................................................................................... viii LIST OF FIGURES .......................................................................................................... ix 1. INTRODUCTION ....................................................................................................... 1 1.1. A brief Overview of Digital Hearing Aid System Architectures and Issues .......................................................................................... 2

1.2. Proposed Directional Digital Hearing Aid System Architectures ...... 8 1.3. Contributions: FDDA based MEMS interface Circuit, self calibrating DAC for an adaptive power scaling ADC. ..................................................... 14

1.4. Thesis Outline ..................................................................................... 14 2. SYSTEM ARCHITECTURE FOR MEMS MICROPHONE INTERFACE.......... 15 2.1. Overview of the MEMS Interface System Architecture ................... 15 2.2. CMOS MEMs Microphone ............................................................... 16 2.3. MEMs Microphone Behavioral Model ............................................. 19 3. OVERVIEW OF SENSING CAPACITANCE ARCHITECTURES ..................... 23 3.1. Overview of Capacitive Sensing Architectures ................................. 23 3.2. Proposed MEMS Microphone Interface Architecture ...................... 25 3.2.1. CTV Architecture Based on FDDA .............................25 3.2.2. Fully Differential Difference Amplifier(FDDA) .........28 3.2.3. Microphone Interface System Analysis .......................33

vi Chapter ................................................................................. Page 3.2.4. Microphone Interface Simulation Results ...................33 3.2.5. MEMs Microphone and MEMs Interface Noise Analysis........................................................................36

4. ANALOG FRONT END ARCHITECTURE AND CIRCUIT ............................... 38 4.1. Analog Front End(AFE) Architecture Overview .............................. 38 4.2. Variable Gain Amplifier Design ........................................................ 39 4.3. 4 th -order CT Σ∆ ADC Architecture ................................................... 44 4.3.1. Behavioral Model of the 4 th -order CT Σ∆ ....................47 4.3.2. Amplifier Non-idealities ..............................................49 4.3.3. Feedback DAC Non-idealities ....................................52 4.3.4. Clock Jitter and Excess Loop Delay ............................52 4.4. 4 th -order CT Σ∆ ADC Circuit Design ................................................ 56 4.4.1. 4 th order CT Loop Filter Design ..................................56 4.4.1.1.1. Input Stage Active RC integrator ............................56 4.4.1.2. g m -C integrator ............................................................57 4.4.1.3. Design g m -C integrator for the NTF Zero ...................58 4.4.2. Quantizer Design .........................................................60 4.5. Proposed Feedback DAC Architecture............................................. 62 4.5.1. First Feedback Design and Self Calibration ................64 4.5.1. Other Feedback DAC Design .....................................73 5. TEST SETUP AND MEASUREMENT RESULTS................................................ 76 6. CONCLUSION AND FUTURE WORKS ............................................................... 82

vii Chapter ................................................................................. Page

REFERENCES ................................................................................................................ 83

viii

LIST OF TABLES Table Page 1: Typical architectural requirements for Digital Hearing Aids .............................8

2: Noise parameters for the Audio Signal Chain ..................................................11 3: Block Specifications for the DHA ...................................................................13 4: CMOS MEMS Microphone Characteristics ....................................................17 5: FDDA Noise Summary Report ........................................................................36 6: Coefficients of the proposed loop filter ...........................................................46

ix LIST OF FIGURES Figure Page 1: A Typical Digital Hearing System......................................................................2

2: A Polar plot of two directional microphones with mismatch in the audio signal path ...........................................................................................................................5

3. Power spectral density of the noise floor in a quite environment. ......................6 4: Power spectral density of the noise floor in noisy environment. .......................7 5: The proposed dual channel DHA Architecture ..................................................9 6: The audio signal chain from input sound pressure in dB SPL to digital bits ..11 7. MEMS Microphone and Preamplifier. ............................................................15 8. 3D view of the MEMS Capacitive Microphone ..............................................17 9. Microphone capacitance change with respect to DC bias. ...............................18 10. Acoustic characterization curve of the MEMS microphone ...........................19 11. Parallel Plate representation of a MEMS Microphone ...................................20 12. First order Electrical Model of the MEMs Microphone .................................22 13. Output response of the MEMs variable cap model .........................................22 14. FDDA based MEMS interface circuit............................................................27 15. Block diagram of a fully differential difference amplifier..............................29 16. Schematic of the Fully differential difference amplifier .................................31 17:. FDDA open loop gain and phase margin simulation results .........................32 18. Dynamic Range Simulation Results ...............................................................34 19. . THD of the differential output @ 1.05kHz ...................................................34

x

Figure Page 20. Transient Simulation Results of the Full Signal Path including the VGA with 105 dB SPL input ...................................................................................................35

21. Block diagram of the Analog Front End .........................................................38 22. Gain curves for the VGA for the three different power/SNR settings. ...........40 23. Block diagram of the VGA, MRC and the feedback resistor .........................41 24. VGA output Noise Scaling for different values of the Feedback resistor, .....42 25. Class B OTA for the VGA .............................................................................43 26. Block diagram of the 4 th order CT sigma delta ..............................................46 27. Power Spectral density plot of the ideal 4 th order CT Sigma Delta ...............47 28 Coefficient Sensitivity Analysis .....................................................................48 29. Block diagram of the Σ∆ ADC with Macro models for the opamp and DAC50 30. SQNR degradation Vs the gain of the Amp Active RC amplifier varies ......51 31:, Modeling the effect of clock jitter on the DAC Current pulse ......................52 32:, Matlab Simulation showing the impact of jitter on the SNR of the ADC .....54 33. Clock waveforms depicting the excess loop delay impact on RZ DAC vs NRZ DAC ..............................................................................................................55

34:, Fully differential folded cascode opamp used in the Active RC integrator. ..58 35:, Fully differential folded cascode gm used in the gm-C integrator. .............59 36:, Fully differential folded cascode gm used in the local zero gm-C integrator59 37. 3- level Quantizer and Schematic of the comparator .....................................61 38. Timing diagram of the Quantizer ...................................................................62

xi Figure Page 39 A high level representation of the proposed feedback DAC Architecture .....63

40 Basic Self Calibration Scheme........................................................................66 41 Proposed Self Calibration Scheme..................................................................68 42. Schematic diagram of the first DAC ...............................................................69 43. Feedback DAC input referred noise ...............................................................70 44. Feedback DAC1 SNR for different current settings ......................................71 45. Feedback DAC input referred noise ...............................................................72 46. Schematic diagram of the other feedback DACs (2,3 &4) .............................73 47. Transient simulations of the common mode keeper showing the glitches being generated in the zero state . ..........................................................................74

48. Impact of the DAC4 nonlinearity to the performance of the Modulator. .....75 49. Test setup for measurement and evaluation of the DHA/ SD ADC ...............76 50. Die photos of the DHA System depicting the (a) The Dual Channel Implementation (b) Single channel details showing the VGA, Active RC and DACs......................................................................................................................77

51: Measured SNR in dB Vs input Signal Amplitude. ........................................79 52: Measured transfer curve of the Sigma Delta ADC showing no peaking and channel gain flatness. .............................................................................................79

53: Measured transfer curve of the Sigma Delta ADC showing no peaking and channel gain flatness. .............................................................................................80

xii Figure Page 54: Measured 2 nd order harmonic distortion of a) without calibration enabled b) with calibration enabled. ........................................................................................81

1 CHAPTER 1 1. INTRODUCTION

Hearing loss afflicts approximately 10% of the world population; the basic solution is amplification of sound to compensate for acoustic signal loss in the ear. Hearings aids can be either analog or digital, with the current advances in digital chip design and digital signal processing technologies, digital hearing aids have become prevalent. One of the fundamental challenges for hearing impaired is speech intelligibility in presence of background noise. The ability to understand speech in a noisy background is expressed as signal-to-noise ratio for comprehending 50% for speech namely SNR-50. In hearing impaired the SNR-50 could be as much as 30dB higher than normal people to achieve the same level of speech comprehension [1]. As such background noise reduction and increasing speech intelligibility is a key challenge for hearing aid design. This thesis presents the implementation and characterization details of a dual channel analog front-end (AFE) for digital hearing aid (DHA) applications that uses novel Micro Electro-Mechanical Systems (MEMS) audio transducers and ultra-low power scalable A/D converters, which enable a very-low form factor, energy-efficient implementation for next generation DHA. The key contribution of the thesis is the implementation of the MEMS microphone interface circuit and power scalable Σ∆ ADC system with self calibrating feedback DAC.

2 1.1. A brief Overview of Digital Hearing Aid System Architectures and Issues The first generation of hearing aids consisted of analog variable gain amplifiers, electret microphones and speakers that compensated for hearing loss. These hearing aids dissipated a considerable amount of power and had flat frequency characteristics that made these devices uncomfortable for most patients. Human hearing and speech sensitivity of human ear is non uniform across the audio frequency band and as such the human hearing loss also varies non uniformly with frequency[1]. The next generation of devices adopted analog filter banks in which band-pass filters were used in parallel to amplify the acoustic signal to a specific level in each different frequency band. This design, however, resulted in bulky devices that still required high power consumption [2]. A major breakthrough was achieved through the development of DHAs that exploited the power of digital signal processors (DSPs) that allowed full programmability and customization to a patient’s hearing characteristic [3- 7].

Figure 1: A Typical Digital Hearing System

3 A typical single channel DHA system, shown in Fig. 1, consists of a Microphone interface circuit, an analog front end (AFE), DSP, followed by digital to analog (DAC) converter and a speaker driver. The AFE consists of a Variable Gain Amplifier (VGA) and an Analog to Digital Converter (ADC). The receiver front end receives the processed digital signal from DSP and converts it to the analog domain. At the backend, a speaker delivers the acoustic sound to excite the patient’s eardrums. The current generation DHA’s employ microphone arrays combined with adaptive array processing that improve audio quality and perception in real-life environments through noise cancellation mechanisms. Such directional DHAs exploit the use of multiple microphone arrays (MMAs) to provide the patient with information on the spatial position of the desired acoustic source, while attenuating the ambient noise at the same time [8]. MMAs apply adaptive beam forming techniques to estimate the signal direction and cancel ambient noise [9-10]. Such directional gain enhancement is quantified through the directivity index (DI). In short directivity index is a measure of the directionality of a MMA system which is measure of speech intelligibility by enhancing the gain of the signal coming from the direction of the desired source, while suppressing noise from other directions. Directivity index is given by eq 1. 1

4

= 10

log

( ℎ

)

The figure 2 shows the response of two directional microphones as a function of the angle of sound incidence, the desired sound directions is at an azimuth angle of 0 0 . The concentric reference lines starting from the centre of the polar plot are graduated in decibels. As the mismatch increases the directivity of the system starts to degrade. For example, to achieve 10 dB of background noise cancellation, the gain of the two transmitter front-ends should match within or less than 0.5 dB [8]. MMA hearing systems require precise adaptive matching of the gain and phase responses of both of the audio transducers and the analog front ends of each channel. Any mismatch affects the directionality The gain mismatch is a cumulative effect of the gain mismatches in the microphone, the microphone interface circuit and the AFE.

5

Figure 2: A Polar plot of two directional microphones with mismatch in the audio signal path The dynamic range and power level of an audio signal have different characteristics in different environments. As illustrated in Fig. 2(a), the audio spectrum of a conversation in quiet environments shows that the noise floor is at about 0 dB-SPL (dB Sound Pressure Level), and the acoustic signal has a 65-dB dynamic range. Fig 2(b) shows the spectrum of the same conversation in a noisy environment (i.e., street) where the noise floor has increased to 25 dB-SPL and the dynamic range is now only 55 dB. Clearly, to cope with the ambient noise, the person who is speaking raises his voice level, but only up to the level of comfortable hearing.l. Consequently, it is clear that changes in signal power, dynamic range and noise floor – can all be exploited to optimize the AFE circuit power consumption. In fact, in high background noise

environments, the DHA system can decide to relax the front performanc e and optimize its parameters to avoid degradation (i.e., clipping) of the high sound architectures have a fixed front dB) to cope with different ambient noise condition power consumption. Figure

Figure

The exist ing DHAs are plagued with three major issues namely 1. The quick degradation of performance in noisy environments in which the AFE becomes saturated due to the ambient acoustic content and background noise. Background noise interferes with the desired conv ersation thereby impairing intelligibility. a very high dynamic range AFE can help relieving this problem, it comes at the expense of high power consumption and complexity. 2. The cumulative gain mismatch in the audio signal path in case of multiple microphone based implementation used in directional DHA’s , degrades the directionality that can be achieved. 3. In current DHA’ electret microphones; however their large size prohibits the application of

8 MMA techniques in completely in-the-ear-canal systems, plus they tend to exhibit a high level of gain mismatch severely impacting the directivity index. 1.2. Proposed Directional Digital Hearing Aid System Architectures The proposed architecture adapts to noise floor conditions by adjusting system linearity and SNR of the Analog Front-End (AFE) to maintain optimal performance. This architecture can optimize power consumption depending on the ambient conditions, thereby maximizing battery life. However, changing the system architecture to scale SNR can lead to transient artifacts, such as clicks or pops, or potential system instability. These issues have been also addressed in this work. The design requirements for a typical hearing aid are summarized in Table I

Table 1: Typical architectural requirements for Digital Hearing Aids

Parameters Value Frequency Range 300Hz to 10KHz Input Amplitude 0 to 120 dB SPL Dynamic Range 120 dB Harmonic Distortion

Input Amplitude < 80 dB SPL < 0.001% (60 dB) Input Amplitude > 80 dB SPL < 0.01% (40 dB) Equivalent Input Noise Level 29 dB SPL Area/Size Small Power Source 1.2 V supplied by zinc-air cell based battery

9 The implemented DHA architecture is shown in Fig. 4. The incident acoustic waves on the dual MEMS microphones are converted into capacitive variations. A microphone interface circuit (i.e., C2V in Fig. 4) translates the capacitive variations into an electrical signal. A VGA is employed to set the optimal voltage level for the following ADC stage. An adaptive dynamic range fourth-order continuous time Σ∆ modulator is employed as the ADC. Ambient noise reduction and directivity can be achieved through manipulation of the phase information of the two incoming channels in the back-end DSP and are adjusted to each individual patient’s hearing needs. It should be noted here that the back-end DSP has not been implemented as part of this thesis. This system implements power/SNR scalability at the AFE to maximize battery life and optimize noise performance. Furthermore, in the following sections it will be shown how the adopted scaling technique avoids transient noise glitches in the RFE, which can lead to user’s ear

Figure 5: The proposed dual channel DHA Architecture

10 fatigue and hearing discomfort. It additionally implements a MEMS interface circuit based on fully differential difference Amplifier (FDDA), which not only converts the audio signal into electrical (voltage) but also provides a single- ended to differential conversion. The audio signal which is essentially sound waves causing a change in the atmospheric pressure around its mean value. This variation in atmospheric pressure is transduced by the MEMS microphone into capacitance changes which are in turn converted to voltage by the FDDA based interface circuit. The voltage signal then gets amplified by the VGA to optimum amplitude level to achieve the maximum dynamic range for the ADC. The amplified signal is oversampled by a Σ∆ AD and converted into 2-bit digital stream. This digital signal is converted into 16-bit signal by a decimation filter which is processed by the DSP. Each stage of this audio signal chain adds thermal and flicker noise to the signal, while the ADC also adds quantization noise and the oscillator’s phase noise is another source of degradation for the SNR. The audio signal chain is designed in order to minimize the noise and maximize the SNR. The noise affecting every stage is either thermal noise or flicker noise; while the microphone is affected by mechanical/Brownian noise while since the BW of interest is from 300Hz to 10 KHz, the flicker noise tends to dominates. Fig 5 shows the full audio signal chain which converts the input sound pressure in dB SPL to digital bits with the additive noise input referred components at every stage. The quantization noise (q noise ) of the ADC and the phase noise (φ noise ) of the clock source.

11

Figure 6: The audio signal chain from input sound pressure in dB SPL to digital bits The input sound pressure level P si has range from 0 to 120 dB SPL, while the microphone sensitivity S mic is essentially the ratio of the capacitive change (δC) over the nominal capacitance (C mic ) of the biased MEMs microphone expressed in dBV/Pa. The parameters given in Figure 5 are defines as below (

,

)

output noise of the MEMs microphone (

,

)

input referred noise of the FDDA (

,

)

input referred noise of the VGA (

,

)

input referred noise of the ADC q noise quantization noise. Φ noise

phase noise of the clock

Table 2: Noise parameters for the Audio Signal Chain

12 Sound applied to a microphone is expressed as sound pressure level (SPL) with reference to hearing threshold of human ear (P o = 20 .10 -6 Pa) [2] which can be expressed in decibels (dBSPL) as follows

(

) = 20 log

(

)

(1.2)

Where P si is the sound pressure level incident on the microphone’s deflecting membrane. To calculate resultant voltage signal, the dBSPL needs to be converted to dBPa which is sound pressure level in decibels normalized to 1 Pascal (Pa) given as follows

=

+ 20

〖 20

. 10

(1.3)

=

− 94

(1.4)

Now this sound pressure level incident on the microphone in terms of the absolute pressure is converted to voltage as a function of the sensitivity of the microphone (S mic ) given as

=

− 94 +

(

)

(1.5)

The sensitivity of conventional electret microphones reported is around -44 dB/V/Pa [2], for the MEMS microphone used for the sensitivity is around the same about -45 dBV/Pa refer to figure 9, in chapter 2. Hence the voltage out (V mo ) of the microphone feeding into the microphone interface circuit and the AFE is given as below

= 10

(1.6)

13 The noise requirements at the input of the ADC are determined by the input signal level which is a function of the input reference level which was set to -0.5V to +0.5V, governed by the given below equation

= 20 log

,

,

(1.7)

Although the full audio dynamic range is 120 dB, but the useful hearable audio dynamic range is about 65 dB.

Microphone Sensitivity (dBPa/V) -45.00

Sound Pressure Level (dBSPL) 0.00

120

Sound Pressure Level (dBPa) -94.00

26

Microphone Out(dBV) - 139.00

-19

Microphone Out(V) 0.00

0.112

Blocks Values

Units Σ∆ Σ∆Σ∆ Σ∆ ADC

Input level (max) @ the ADC 0.50 V Dynamic Range of ADC 70.00 dB Total noise @ the input of ADC 55.90 uVrms

Vnoise 39.53 uVrms

VGA

VGA Gain 40.00 dB VGA Input Noise 15.81 uVrms

FDDA MIC Circuit

FDDA Transducer Gain 6.00 dB FDDA Input Noise 85.00 uVrms

FDDA Input Noise 12.57 dB SPL Signal to Noise Ratio 68.43

Table 3: Block Specifications for the DHA

14 The full signal chain is able to achieve more than 65dB SNR which is required to meet the comfort zone for audible sound as shown in figure 3.

1.3.Contributions: FDDA based MEMS interface Circuit, self calibrating DAC for an adaptive power scaling ADC. The contributions of this thesis are the development and implementation of FDDA based MEMS microphone interface circuit based on C2V conversion, and a self calibrating feedback DAC to for a power scalable ADC.

1.4.Thesis Outline The rest of the thesis presents the implementation details of the proposed dual channel Digital hearing Aid (DHA). Chapter 2 focuses on the system architecture for the MEMS interface circuit design, which develops a MEMs microphone behavioral model for designing the Fully differential difference amplifier (FDDA). Chapter 3 presents the Analog front end architecture including the Variable Gain Amplifier, the power scalable ADC, and the self calibrating feedback DAC. Measurement setup and results are presented in chapter 4. Chapter 5 presents the conclusions and future work.

15 CHAPTER 2 2. SYSTEM ARCHITECTURE FOR MEMS MICROPHONE INTERFACE

CMOS MEMS Microphone with their small size and ease of integration with CMOS signal processing chain present opportunities for design of highly integrated DHAs. Furthermore CMOS MEMS microphone are also becoming increasing competitive in terms of price and performance with their electrets counterparts. A CMOS MEMS microphone simply consists of a moveable plate and a stiff back plate which forms a variable capacitor. 2.1.Overview of the MEMS Interface System Architecture

The proposed system consists of a MEMS microphone which is essentially capacitive and low-noise low offset microphone preamplifier with a high input impedance and balanced input. interface with a low noise The MEMS microphone is biased by a DC voltage; the incident acoustic waves causes the Figure 7. MEMS Microphone and Preamplifier.

16 capacitance to vary which is converted to a voltage and amplified by the MIC preamplifier as shown in Fig 7. The preamplifier needs to have a very high input impedance to be able to detect the acoustic signal without being affected by the impedance of the MEMs microphone. A low input offset and low input referred noise is required to ensure that the maximum gain can be used without getting swamped by the offset. Additionally the input amplitude of the signal can vary from 20uV to 100mV with at least SNR for about 14 dB. 2.2.CMOS MEMs Microphone This section describes the MEMS microphone designed and developed by the MEMS group at Arizona State University (ASU).. Fig. 3 depicts the construction of the capacitive MEMS microphone that was used in the DHA design. The device size is 2.5x2.5x0.5 mm 3 and it consists of a multi layered parylene diaphragm suspended over a silicon substrate [11-13]. This MEMS microphone has three major parts the top and bottom electrodes which detect the capacitance change, the Ag (anode) and the Ni(cathode) which are electrically modulated as result of a phenomenon called electro deposition. The 1µm gap between the diaphragm and substrate forms a parallel plate capacitor, where as the sound pressure level causes a deflection in the diaphragm causing changes in the capacitance. The substrate acts as the capacitor back plate and acoustic holes are etched from the backside of the substrate to let the air in the gap move freely. This MEMS microphone has the additionally property that its capacitance can be

17 adjusted by applying a tuning voltage as a result of the electrochemical reaction that takes place causing the movements of Ag + ions.

This feature of the Microphone is used for tuning any gain mismatches in two microphones. Fig. 5 shows the measured capacitance change as the DC voltage bias is swept from 100 mV to 900 mV. When the DC bias voltage is in the

Figure 8. 3D view of the MEMS Capacitive Microphone

CMOS MEMS Microphone Parameter Value Units size 2.25x2.25x0.5

mm 3

Capacitor Gap 1 um Sensing Capacitance 20 pf Capacitance Sensitivity 20 ff/mV

Table 4: CMOS MEMS Microphone Characteristics

18 700-900 mV range, the capacitance change of the microphone peaks and saturates around 100fF. The 200fF data point is an outlier in fig. 7. The capacitance change is converted to voltage signal by a capacitance-voltage interface, which will be discussed in section 2.3. Fig. 8 shows the acoustic response of the MEMS microphone. A 1 kHz acoustic signal with 20 to 80 dB SPL (sound pressure level) was applied to the MEMS microphone

Figure 9. Microphone capacitance change with respect to DC bias.

19

2.3.MEMs Microphone Behavioral Model The miniscule capacitance variation of the order of tens of femto farads, generated by the MEMS microphone due to an acoustic signal is then converted into an electrical signal by a capacitive interface circuit. The design of the interface circuit presents unique challenges due to the small

Figure 10. Acoustic characterization curve of the MEMS microphone

20

sensing capacitance, the high output impedance, robust DC bias requirements, and circuit noise (mechanical and electrical). A typical MEMS condenser microphone needs to be connected to a bias voltage source through a high impedance [14]. To first order, the MEMS microphone can be modeled as a variable capacitor. Sound pressure moves one side of the parallel plate capacitor, creating a capacitance change, as given in the Figure 9. For a MEMS microphone biased by a DC voltage V bias , the charge Q(t) vs. voltage V(t) relationship of a capacitor C MIC (t) is expressed by

(

) =

(

)

(

)

(2.1)

(

) =

_

+ ∆

(

)

(

)

(2.2)

Figure 11. Parallel Plate representation of a MEMS Microphone

21 Where C MIC is the total capacitance of the MEMS Microphone, while C MIC_DC is the nominal capacitance value at certain bias V bias . ∆C is the change capacitance caused due to the acoustic excitation of the MEMS Microphone, Vc is the electrical equivalent of the acoustic signal. The sensed voltage of a MEMS microphone can be derived from (3), by applying the charge conservation law,

= ∆

(

)

_

+

(2.3)

where C p is the parasitic capacitance associated with interconnect etc. The sensitivity of the MEMs microphone is given as below

=

(

) (

+

) ∆

(2.4)

where ∆P is the change in sound pressure in Pascal, whereas Sensitivity has the units of dBV/Pascal A basic electrical veriloga model was developed for the MEMS microphone based on the characteristics of the microphone as depicted in the curves in Figure 7 & 8. This basic electrical model of the MEMs microphone consists of a fixed capacitor C MIC_DC and a variable Capacitor C v which is modulated by the sound pressure level, while R N represents the electrical equivalent of the acoustical noise of the microphone, and C P being the parasitic capacitors.

`

22

For this model the acoustic noise is assumed to be minimal. Actual measurements of the acoustic noise of the MEMS microphone is around 20 dBSPL. A detailed noise analysis is presented in the next chapter..

Figure 12. First order Electrical Model of the MEMs Microphone

Figure 13. Output response of the MEMs variable cap model Generic Variable Cap Model 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -2.50 -2.00 -1.50 -1.00 -0.50 0.00 0.50 1.00 1.50 2.00 2.50 Vctrl(V) Capacitance (pF)

23 CHAPTER 3 3. OVERVIEW OF CAPACITIVE SENSING ARCHITECTURES 3.1.Overview of Capacitive Sensing Architectures Capacitive sensing converts mechanical displacement or motion of the surfaces forming the capacitance into an electrical based signal like voltage or current or a time based signal like frequency or time period. In this thesis we are focused on electrical based schemes which can generate voltage or current as an output. Capacitors can sense ac signals only, as such ac modulation sources are required for capacitive sensing. Capacitive sensing generates an AM signal that needs to be sampled or demodulated, to extract its envelop. Capacitive sensing can be single ended or differential. Differential capacitive sensing has all the advantages associated with differential signaling. Capacitive sensing only uses the parallel-plate part of the total CMOS MEMS capacitor as the useful part, while the fringe part adds to the parasitic capacitance. The other major non Idealities for CMOS MEMS capacitive sensors are Brownian Noise of the MEMS device • Electronic/Circuit Noise o 1/f noise o Thermal noise • Circuit offset • Sensor Offset • Undesirable Charging • Parasitic Capacitance

Full document contains 98 pages
Abstract: A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems (MEMS) microphones and an adaptive-power analog font end (AFE) is presented. The Microphone interface circuit based on FDDA converts the capacitance variations into voltage signal, achieves a noise of 32 dB SPL (sound pressure level) and an SNR of 72 dB, additionally it also performs single to differential conversion allowing for fully differential analog signal chain. The analog frontend consists of 40dB VGA and a power scalable continuous time sigma delta ADC, with 68dB SNR dissipating 67uW from a 1.2V supply. The ADC implements a self calibrating feedback DAC, for calibrating the 2 nd order non-linearity. The VGA and power scalable ADC is fabricated on 0.25 um CMOS TSMC process. The dual channels of the DHA are precisely matched and achieve about 0.5dB gain mismatch, resulting in greater than 5dB directivity index. This will enable a highly integrated and low power DHA.