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Electron microscopy studies of defect structure and correlated impurity incorporation in silicon and germanium nanowires

Dissertation
Author: Eric R. Hemesath
Abstract:
Conventional and scanning transmission electron microscopy (TEM) were employed to investigate defect structures and catalyst impurity incorporation in silicon and germanium nanowires grown via the vapor-liquid-solid (VLS) mechanism. Novel synthesis and sample preparation procedures were developed that enabled advanced characterization of nanowire composition and structure. For the first time, conclusive evidence was shown for a finite concentration of Au impurities in Si nanowires grown by the VLS mechanism. Ordered arrays of stacking faults in Si nanowires were found to give rise to new polytypes that had not been previously identified. A novel syntaxial growth mechanism, resulting in simultaneous one-dimensional growth of Mn11 Ge8 /Ge nanowire heterostructures from a shared growth interface, was investigated. Analytical TEM, electron diffraction and high resolution TEM (HRTEM) were used to identify the germanide and to establish the crystallographic relationships between the two crystals, including epitaxial and fiber textures. Aberration-corrected scanning TEM (STEM) was used to show that individual gold catalyst atoms are incorporated into Si nanowires on sites associated with planar defects and in defect-free regions. Cross-sectional imaging of individual nanowires was used to establish that gold atoms were incorporated on internal grain boundaries in bicrystalline nanowires, and in some cases appear to be associated with dislocations at the defect plane. STEM tomography revealed that defective nanowires appear to crystallize from a faceted growth front and suggested a correlation between interface shape and the position of Au columns in the wire interior. HRTEM and electron diffraction were used in correlation with Raman spectroscopy to study the ordering of {111} defect arrays in Si nanowires. Stacking faults were found to occur in periodic arrangements corresponding to the 9R rhombohedral and 2H hexagonal polytypes. Cross-sectional imaging was used to establish the origins and strengths of forbidden reflections arising from ordered stacking faults and twinned nanowires.

8 Table of Contents ABSTRACT 3 Acknowledgements 5 List of Tables 11 List of Figures 12 Chapter 1.Introduction 16 Chapter 2.Synthesis and design of Si and Ge nanowire heterostructures of controlled taper 24 2.1.Vapor-Liquid-Solid growth of semiconductor nanowires 24 2.2.Design of growth processes to enable reliable atom probe tomography analysis 27 2.2.1.Anisotropy control 29 2.2.2.Heterostructure formation 33 2.2.3.Substrate preparation methods 38 2.2.3.1.Epitaxial growth for vertically oriented nanowires 38 2.2.3.2.Density control 40 Chapter 3.Electron microscopy characterization of semiconductor nanowires 44 3.1.Nanowire sample preparation for electron microscopy 44 3.1.1.Solution dropcasting 45 3.1.2.Preparation of nanowires for electron tomography 46 3.1.3.Preparation of nanowire cross-sections 48 3.2.Electron microscopy of semiconductor nanowires 52

9 3.2.1.Electron diffraction of nanowires 52 3.2.2.High resolution TEM imaging of nanowires 55 3.2.3.Scanning transmission electron microscopy 57 3.2.4.Analytical electron microscopy 59 Chapter 4.Texture analysis of syntaxial nanowire heterostructures 62 4.1.Introduction 62 4.2.Description of nanowire growth 63 4.3.Identification of nanowire composition and structure 65 4.3.1.Composition analysis 66 4.3.2.Structure analysis 68 4.4.Crystallographic relationships between Ge & Mn-germanide nanowires 74 4.4.1.Texture analysis 75 4.4.2.Texture analysis in nanowire heterostructures 78 4.5.Conclusions 83 Chapter 5.Structural investigation of polytypes in Si nanowires by correlated Raman spectroscopy and TEM 84 5.1.Crystallography of defects commonly observed in nanowires 85 5.1.1.Previous characterization reports in nanowire systems 87 5.1.1.1.Group III-V nanowires 87 5.1.1.2.Group IV nanowires 89 5.2.Correlated Raman and TEM characterization of polytype phases on individual Si nanowires 91 5.2.1.Defect evolution within a single nanowire 91 5.2.2.Identification of polytype phases 93 5.2.2.1.Mixed polytype phases 93 5.2.2.2.2H polytype 95 5.2.2.3.9R polytype 97 5.2.2.4.Random stacking fault arrangement 99 5.3.Conclusions 101

10 Chapter 6.Conclusive determination of the structural origin of kinematically- forbidden diffraction effects 102 6.1.Cross sectional analysis of nanowire with forbidden reflections in DP 103 6.2.Cross section of defective wire with [110] growth direction 107 6.3.The structural origins of anomalous diffraction spots 111 6.3.1. 1 3 {422} forbidden reflections 111 6.3.2.3 ×{111} superstructure periodicity 116 6.4.Conclusions 119 Chapter 7.Detection of Au catalyst impurities in Si Nanowires 120 7.1.Background 121 7.2.Au impurity imaging using aberration-corrected STEM HAADF imaging 123 7.3.Three-dimensional localization of Au atoms using depth sectioning 126 7.4.The influence of Au incorporation on Si nanowire transport properties 132 7.5.Summary 135 Chapter 8.An investigation of Au impurity trapping at defect interfaces in Si nanowires 136 8.1.Introduction and motivation 136 8.2.Determination of defect structure and Au occupation sites in individual Si nanowires 139 8.2.1.Au segregation to a grain boundary interface 139 8.2.2.Au trapping at an incoherent defect plane 144 8.2.3.Investigation of the growth interface shape of a defective Si nanowire 149 8.3.Implications for the growth of high purity Si nanowires from the VLS process153 8.3.1.Nanowires with [111] growth directions 154 8.3.2.Nanowires with [112] growth directions 155 8.3.3.Nanowires with [110] growth directions 157 Chapter 9.Summary and future directions 160 References 164

11 List of Tables 2.1 Varying degrees of taper accomplished for several growth experiments.32 2.2 Growth conditions that provide highest yield of epitaxial wires for both Ge and Si.40 4.1 Material properties of Ge and germanide phases.70

12 List of Figures 2.1 Au-Si phase diagram.26 2.2 Nanowire heterostructures demonstrating varying degrees of taper.30 2.3 Si nanowires with axial dopant modulation.36 2.4 Boron-doped Si heterostructure analyzed by atom probe tomography.37 2.5 Epitaxial growth of Ge nanowires on a Si(111) micropost substrate.39 2.6 Epitaxial growth of Si nanowires on Si(111) substrates.43 3.1 Two different approaches to nanowire sample preparation for electron tomography.48 3.2 FIB procedure from producing nanowire cross-sections.51 3.3 Determination of nanowire growth direction.54 3.4 Schematic of depth-sectioning in STEM.59 3.5 Schematic illustrating the electronic transitions exploited in analytical electron microscopy.61 4.1 Mn islands and GeNWs.64 4.2 Mn-Ge phase diagram.65 4.3 STEM EDS mapping of Ge/Mn-germanide nanowires.67

13 4.4 Spectrum imaging of leader.68 4.5 High resolution TEM images of GeNWs.69 4.6 Representative example of beam damage to a Mn-germanide leader.72 4.7 Diffraction data of Mn 11 Ge 8 leader crystals.73 4.8 TEM images demonstrating the orientation of leader crystals.75 4.9 Diffraction analysis of crystallographic relationship between nanowire and leader.76 4.10 Example of a texture which appears random.79 4.11 Example of epitaxial texture in the Mn-germanide/Ge heterostructure.81 5.1 TEM image of a GaP nanowire.88 5.2 HRTEM images of defective Si nanowires.90 5.3 Defect structure evolution during growth of a Si nanowire.92 5.4 Defect structure of a nanowire with mixed polytypes.95 5.5 Structural characterization of a nanowire with predominant a 2H polytype structure.96 5.6 Structural characterization of a nanowire with predominant a 9R polytype structure.98 5.7 Structural characterization of a nanowire with a disordered arrangement of stacking faults.100 6.1 Observation of 1 3 {422} spots in a Si nanowire diffraction pattern.103 6.2 Cross sectional view of nanowire with polytype inclusion.105

14 6.3 Images comparing the cross-sectional shape of a twinned nanowire and nanowire with a polytypic inclusion.107 6.4 Lattice image showing regions with higher order periodicity.108 6.5 Cross-sectional lattice imaging of a defective wire.110 6.6 Schematic Ewald sphere construction leading to forbidden diffraction spots.114 6.7 Profile of FFTs showing differences in the forbidden peak intensity.115 6.8 TEM image demonstrating an overlapping twin structure.117 7.1 Aberration-corrected STEM HAADF imaging of Si nanowires with Au impurities.124 7.2 Simulated scattering and HAADF images of Au atom in a silicon slab.125 7.3 Three-dimensional localization of Au atoms.127 7.4 HAADF-STEM images of lines of Au atoms at different tilt angles.129 7.5 Atom probe analysis of the catalyst-nanowire interface.131 7.6 Diameter dependence of minority carrier diffusion length.133 8.1 Cross-sectional analysis of a twinned Si nanowire.137 8.2 Scanning and conventional TEM images of a Si nanowire with many axial lines of Au.140 8.3 High resolution cross-sectional imaging of a Si nanowire with columns of Au present in an array at a grain boundary.142

15 8.4 Z-contrast STEM image of a Si nanowire cross-section with atomic lines of Au acquired at an orientation off of a low-index zone axis.143 8.5 Plan view imaging of a Si nanowire with planar defects oriented along the 110 direction.145 8.6 Comparison of plan and cross-sectional views of a defective Si nanowire grown in the 110 direction.147 8.7 Several HAADF-STEM images of a defective nanowire tip from a tilt series acquired for tomographic reconstruction.150 8.8 Cross-sectional imaging of a defective nanowire composed of two bicrystals that share a common faceted interface.151 8.9 Analysis of the cross-sections of the tomographic reconstruction of the growth interface of a defective Si nanowire.153 8.10 Analysis of the cross-sections of the tomographic reconstruction of the growth interface of a defective Si nanowire.156

16 CHAPTER 1 Introduction In 2010,the size of the global semiconductor industry is expected to grow to $291 billion dollars,which represents an increase of nearly 110% since 2002. 1 This incredible growth has been fueled by a continually increasing worldwide demand for more computing speed at a lower power consumption across a number of electronic device platforms.Silicon has served as the industry’s preferred semiconductor for decades because it is abundant, can be mass-produced as one of the purest materials in the world,and has desirable electronic properties. The growth of the semiconductor industry has depended on scaling,that is,the con- tinuous miniaturization of planar devices and supporting architectures that enables in- creasing transistor densities on integrated circuit chips.Scaling has been enabled by impressive feats of engineering in the improvement of top-down techniques such as pho- tolithography.Conventional approaches to the scaling of silicon will reach the ultimate limit within the next decade as device components reach atomic scale dimensions,and new device architectures are sought as replacements.To maintain the profitability of the industry,a consortium of industry experts began publishing annual agendas in the mid-1990s known as the ‘International Roadmap for Semiconductors’ (ITRS) to guide the directions of research and assist in transitioning from the traditional transistor design. As these initial ITRS documents were being published,an influential report appeared that demonstrated reproducible synthesis of crystalline Si and Ge nanowires that were

17 tens of microns in length and 3-20 nmin diameter. 2 Early reports showed that both p-type and n-type nanowires could be synthesized through the in-situ incorporation of dopants during growth, 3 and p-n junctions were demonstrated in GaAs nanowires. 4 Ohmic con- tacts could be made to individual nanowires and field effect transistors were demonstrated. Subsequent studies achieved a level of self-assembly which was exploited to create crossed nanowire logic gates. 5,6 The rapid progress of nanowire research generated a significant amount of attention by establishing the potential for nanowires to be employed as the functional components of next-generation devices.As a result,semiconductor nanowires have been present in every ITRS edition since 2001 as a promising class of emerging re- search materials.These developments sparked a resurgence of interest in semiconductor nanowires,the growth of which was originally explored in seminal research by Wagner 7,8 and Givargizov 9,10 on what were then called ’whiskers’.Wagner is credited with the first identification of impurity-mediated growth of whiskers 7 ,and Givargizov made important contributions to understanding the growth mechanism. Researchers rediscovering the work of Wagner and Givargizov,often through the more recent work of Hiruma,Charles Lieber,Lars Samuelson,and Peidong Yang,quickly re- alized the versatility of the Vapor-Liquid-Solid (VLS) growth mechanism,which will be discussed in more detail in the following chapter.The VLS growth mechanismcan be used to synthesize group IV,III-V,and II-VI semiconductors with control over aspect ratio, density,and position.Nanowires have intrinsically high aspect ratios that can introduce new size-dependent material properties.These unique capabilities provided researchers a new platform to probe new avenues of physics,chemistry,and biology at the nanoscale,

18 and new non-traditional semiconductor devices were created as a result.Some compelling examples include: • Nanometer-scale lasers – By using interactions between plasmons on a metallic surface and a high-gain CdS nanowire,coherent light was generated from optical modes that are 100 times smaller than the optical diffraction limit. 11 • High-performance tunneling diodes – Through the formation of atomically-abrupt axial heterojunctions,quantum dots were created in nanowires that functioned as resonant tunneling diodes in which the emitter,collector,and quantum dot were formed in a single nanowire. 12 • Chemical and biological sensors – Nanowire-based sensors in which the specific binding of biological and chemical species to the channel of a nanowire FET induces a large change in conductance,and thus a high sensitivity. 13,14 • Li-ion battery anodes – A nanowire geometry is more amenable to many repeti- tions of the Li-ion exchange process and can provide a route to use silicon-based anodes in high-performance lithium batteries. 15 • Electronic interfacing with biological materials – Nanowire-based devices can pro- vide a functional interface to detect and stimulate signals in biological cells and tissue,including neurons and cardiac cells. 16–18 These diverse applications demonstrate the versatility of the VLS growth mechanism in the synthesis of functional nanomaterials.In part because VLS growth is so robust and versatile,novel applications of nanowires of new compositions are continuously being demonstrated.Adecade of intense research on semiconductor nanowires has not,however, established a complete bridge between academic curiosity and commercial viability.The

19 most interesting uses of nanowires demonstrated thus far have been ‘proof-of-principle’ devices achieved only at a laboratory scale.One of the major challenges facing “bottom- up” nanomaterials is large-scale integration into circuits and devices.Current top-down fabrication processes can produce a billion functional transistors on a single integrated circuit,and individual nanowire building blocks will need to be assembled to a similarly high density to garner serious commercial attention.This is one of the major obstacles outlined by the ITRS which must be overcome prior to major investment by the semicon- ductor industry.However,it must be stressed that not all nanowire device applications require large scale integration. Another major challenge is controlled impurity doping,as most semiconductor appli- cations require the incorporation of dopants to form contacts and functional junctions. While Ohmic contacts and p-n junctions have been demonstrated in a number of previous reports,very little is known about the incorporation of intentional or unintentional im- purities during VLS growth.Major advances in this area were recently made using atom probe tomography (APT) as reported in the doctoral thesis work of Dr.Daniel Perea. 19 In his work,dopants were intentionally introduced and detected in the small concentrations that are typically used to influence the electronic behavior of Si and Ge.There is also the potential for unintentional incorporation of impurities in metal-mediated VLS growth.In fact,there has been a long-standing concern that unintentional doping from the metal catalyst could severely degrade the electronic properties of VLS grown nanowires,partic- ularly those that depend on long minority carrier lifetimes.While APT was used to map intentional dopants in individual nanowires,no evidence of catalyst atoms was found in the ’bulk’ of the nanowires. 20,21 Catalyst atoms such as gold,however,may influence the

20 electronic properties of nanowires even when present below the detection limit of APT, which has been found to be 5-10 ppm under ideal conditions. 22 In addition to impurities,defects may exert substantial influence over the electronic properties of nanowires.While the ideal growth process would result in perfect uniformity of growth direction and crystallinity,the non-idealities of the VLS growth process have not always been considered,and recently some attention has been paid to the prevalence of structural defects in silicon nanowires. 23,24 While a range of structural defects have been reported,several topics have not received adequate attention,including a thorough identification of their structure,factors influencing their prevalence,and their consequence for nanowire properties. This thesis addresses the unintentional incorporation of catalyst impurities and the occurrence of planar defects in Si nanowires using a multifaceted approach that includes high-resolution scanning and conventional TEMimaging,electron diffraction,and Raman spectroscopy.New approaches to nanowire sample preparation developed by the author and collaborators enabled electron tomography and high-resolution cross-sectional imag- ing of defective nanowires,leading to newunderstanding of the relationship between defect structures and impurity incorporation.It will be shown that correlated measurements are uniquely able to conclusively resolve important defect structures in semiconductor nanowires. In Chapter 2,the principles governing VLS growth of Si and Ge nanowires are dis- cussed.Also described are advances in synthesis that enabled innovative characterization techniques,such as APT,to be applied to semiconductor nanowires.A host of elec- tron microscopy techniques were applied to characterize the structure and composition of

21 nanowires in this work.The details of the application of these techniques are described in Chapter 3.The unique advantages and disadvantages of the one-dimensional geome- try of semiconductor nanowires with respect to electron microscope analysis will also be detailed. In Chapter 4,a novel ‘syntaxial’ nanowire growth mechanism is presented in which a Mn-germanide seed particle was found to mediate the growth of Ge nanowires.A Mn- germanide seed crystal was found to exhibit one-dimensional growth along with the Ge nanowire from a shared growth interface,which is very different from traditional metal- catalyzed VLS growth.Analytical electron microscopy was used to determine the relative composition of synthesis products.HRTEMimaging and electron diffraction were applied to show that the structure of the Ge and Mn-germanide phases were diamond-cubic and orthorhombic Mn 11 Ge 8 ,respectively.Special crystallographic relationships were observed to occur between the Mn-germanide and Ge crystal,and these textures are described. Chapter 5 focuses on the occurrence of planar defects in Si nanowires.In some nanowires oriented along the 112 direction,lamellar {111} stacking faults were observed to run along the entire axis of the wire.Using HRTEM and electron diffraction,it was found that the stacking arrangement of such defects was not always random.Rather,long range order of the stacking faults led to the formation of polytype phases,as established by Raman spectroscopy measurements that were correlated with TEM imaging and elec- tron diffraction on the same nanowires.While Si polytypes have been previously observed in Si thin films,this was the first definitive claim of polytype phases in Si nanowires.

22 Chapter 6 discusses anomalous diffraction behavior that occurs in defective Si nanowires. There are a number of previous reports which aimed to explain the origin of these diffrac- tion effects,and many conflicting hypotheses were suggested.By employing a correlated imaging approach which compares nanowire defect structure in both plan and cross- sectional views,conclusive evidence for the structural features responsible for the anoma- lous diffraction patterns has been attained. Chapter 7 presents scanning transmission electron microscopy (STEM) results on Au- catalyzed Si nanowires.Specifically,high-angle annual dark-field (HAADF) imaging was used to address the nature of unintentional incorporation of Au catalyst impurities in the bulk of Si nanowires.By employing a STEM with spherical aberration correction,single atoms of Au were clearly resolved in HAADF images.Furthermore,the reduced depth of field of the corrected probe enabled the three-dimensional localization of individual atoms.Au atoms were found within the nanowire in excess of expectations based on an estimated solubility extrapolated from the bulk phase diagram. HAADF-STEM imaging showed that Au catalyst atoms could become trapped at axial planar defects in Si nanowires,and the nature of this impurity incorporation is addressed in Chapter 8.It was found that both 112 and 110 oriented nanowires could trap Au atoms,with the latter being more prevalent for the samples studied during this thesis research.Because Au atoms were trapped on defects present on the interior of nanowires with unknown defect structure,high-resolution cross-sectional imaging was used to identify the defect structure responsible for impurity trapping.In all examples studied,nanowires were observed to be bicrystalline with a central grain boundary.Im- perfections on this boundary,such as dislocations or voids,served as the sites for Au

23 segregation.Electron tomography revealed that the growth interface of such wires was not planar,which suggested the position of the Au atomic lines in the wire interior is directly related to the faceting of the growth front.

24 CHAPTER 2 Synthesis and design of Si and Ge nanowire heterostructures of controlled taper In this chapter,the fundamental principles of the vapor-liquid-solid (VLS) growth mechanism are introduced.Following this is discussion of process design principles that were developed by the author to enable control over the taper of Si and Ge nanowire het- erostructures.The control that was achieved over morphology is shown to be essential to a number of advanced characterization techniques,particularly atom probe tomography. 2.1.Vapor-Liquid-Solid growth of semiconductor nanowires Although many approaches to synthesize anisotropic materials have been developed, 25 the focus of this discussion will be the growth of semiconductor nanowires via the vapor- liquid-solid mechanism. 7 In the decades since its discovery in 1964,the VLS growth mech- anism has become one of the most commonly used methods to fabricate one-dimensional crystals because it enables nanowire growth to be carried out over a wide range of ex- perimental conditions and materials systems.Because the VLS growth mechanism can produce nanowires of well-defined morphology and composition,it has been exploited to create building blocks for a wide range of diverse device architectures. 25,26 There are a number of ways to deliver the semiconductor precursor to a VLS catalyst, including laser ablation,thermal and electron-beamevaporation,solution-based synthesis, and molecular beam epitaxy.These approaches are summarized in a review article by

25 Schmidt et al. 27 In comparison with these techniques,chemical vapor deposition (CVD) provides a larger degree of control over certain aspects of growth that are of particular importance to the aims of this thesis work.The majority of the work discussed throughout this thesis was done on Au-catalyzed Si nanowires grown via thermal CVD in a hot-walled tube furnace reactor,so the principles of CVD will be described in detail below. VLS growth requires a metallic impurity particle to promote one-dimensional crys- tallization of a semiconductor.Au colloidal nanoparticles (Ted Pella,Inc.) that range in diameter from 2-150 nm are deposited on a planar substrate,typically single crystal Si.The process is initiated by heating the substrate above the eutectic temperature for the relevant materials,which is 363 ◦ C for the Au-Si system.Next a Si-based precursor is introduced into the growth chamber.Process conditions are chosen such that decomposi- tion of the gas-phase precursor is favored to occur only at the surface of the Au catalyst particle.Upon chemical decomposition,elemental Si incorporates into the particle,form- ing a liquid eutectic droplet.Continued adsorption of the precursor species increases the semiconductor concentration in the droplet until supersaturation is reached.Excess Si precipitates from the droplet at the liquid/solid interface and a crystal is nucleated.The liquid-solid interface serves as both the growth front and the sink for continued crystal- lization of the crystal lattice.One-dimensional growth is sustained in the presence of reactant,and the catalyst droplet remains at the tip of the nanowire throughout growth. The thermodynamic evolution is mapped in the Au-Si phase diagram shown in Figure 2.1. There are several salient aspects of this growth mechanism.First,the dimensions of the nanowire can be controlled.The nanowire diameter is defined by the diameter of

26 Figure 2.1.The sequence of steps in VLS nanowire growth are shown.In step 1 the Au catalyst is heated and exposed to a Si precursor gas.Incorpo- ration of Si into the liquid droplet (step 2) continues until supersaturation is reached.Si crystal nucleation occurs,and growth continues in regime 3 near the liquidus line of the phase diagram. the droplet at the liquid-solid interface,and the length is determined by the duration of the reaction.For example,Si nanowires with uniform electronic properties have been grown to millimeter-scale lengths at an aspect ratio of 100,000. 28 A second advantage of VLS growth is position control.Nanowires will grow only where a catalyst particle is present;if the metal catalyst is patterned in an array,nanowires will grow in a patterned

27 array.A third important feature is that additional components can be incorporated into the crystal by introducing different vapor phase species during growth.This is particularly advantageous in CVDgrowth of nanowires because it allows for in-situ doping of the semiconductor material and the formation of both radial and axial heterostructures. In the following section,it will be shown how these features can be exploited to grow nanostructures of a desired morphology and composition,providing the opportunity for powerful characterization techniques to be applied to these nanoscale materials for the first time. 2.2.Design of growth processes to enable reliable atom probe tomography analysis Reports of semiconductor nanowire synthesis by the VLS process number in the thou- sands,and one can readily find conditions that lead to nanowire growth.However,ob- taining precise control over nanowire morphology and composition requires a deeper un- derstanding of the chemical interactions which occur within the growth chamber.This section is focused on preparation of nanowire samples for atom probe tomography anal- ysis,and the specific objectives for nanowire growth are:a) Control the ratio of axial to radial growth,b) grow heterostructures with controlled composition,taper,and without kinking,c) achieve epitaxial growth,and d) grow nanowires at a controlled areal density. All CVD reactors require gaseous precursors,a reaction chamber,and a heat source. Most CVD growth takes place below atmospheric pressure which implies the use of a vacuum pump,a pressure controller,and mass flow controllers to produce the gaseous

28 environment in the reactor chamber.The reactor used for the thesis work is a low- pressure CVD system with growth pressures ranging from ten to several hundred torr. The reactor chamber is a 1” diameter quartz tube furnace with a 12” hot-zone.Syntheses were carried out using hydride precursors.SiH 4 and GeH 4 (10% in H 2 ) were employed for the growth of Si and Ge nanowires,respectively.B 2 H 6 (100 ppm in He) and PH 3 (200 ppm in He) were introduced in trace amounts to provide p-type and n-type doping, respectively.A bubbler with a manganese source (tricarbonyl methylcyclopentadienyl manganese) enabled Mn to be used both as a dopant and a catalyst for nanowire growth, as will be discussed in Chapter 4.Additionally,carrier gases including N 2 ,He,O 2 ,Ar,and H 2 could be provided to dilute the reactant gases and provide uniform flow dynamics 29 . A Pfeiffer DryPump is located downstream of the pressure controller and can reach base pressures of ∼10 −3 mbar. The most important aspect in achieving nanowire growth of specified morphology is having the ability to controllably influence the precursor decomposition kinetics through- out the reaction chamber.This is complicated by a number of factors.First,precursor decomposition is thermally activated,and each species will have distinct activation barrier for dissociation.Growth can be simplified by matching precursors with similar kinetic behavior.Second,the temperature along the 12” hot-zone of the furnace is not constant. A uniform hot-zone is maintained in the central 6” of the furnace,and temperature gra- dients exist at the upstream and downstream ends of the growth chamber.This has a direct influence on the temperature profile of the gases in the growth chamber,and often times leads to non-uniform decomposition as a function of distance in the growth tube. Finally some precursor species,such as B 2 H 6 ,are very reactive and can induce additional

Full document contains 177 pages
Abstract: Conventional and scanning transmission electron microscopy (TEM) were employed to investigate defect structures and catalyst impurity incorporation in silicon and germanium nanowires grown via the vapor-liquid-solid (VLS) mechanism. Novel synthesis and sample preparation procedures were developed that enabled advanced characterization of nanowire composition and structure. For the first time, conclusive evidence was shown for a finite concentration of Au impurities in Si nanowires grown by the VLS mechanism. Ordered arrays of stacking faults in Si nanowires were found to give rise to new polytypes that had not been previously identified. A novel syntaxial growth mechanism, resulting in simultaneous one-dimensional growth of Mn11 Ge8 /Ge nanowire heterostructures from a shared growth interface, was investigated. Analytical TEM, electron diffraction and high resolution TEM (HRTEM) were used to identify the germanide and to establish the crystallographic relationships between the two crystals, including epitaxial and fiber textures. Aberration-corrected scanning TEM (STEM) was used to show that individual gold catalyst atoms are incorporated into Si nanowires on sites associated with planar defects and in defect-free regions. Cross-sectional imaging of individual nanowires was used to establish that gold atoms were incorporated on internal grain boundaries in bicrystalline nanowires, and in some cases appear to be associated with dislocations at the defect plane. STEM tomography revealed that defective nanowires appear to crystallize from a faceted growth front and suggested a correlation between interface shape and the position of Au columns in the wire interior. HRTEM and electron diffraction were used in correlation with Raman spectroscopy to study the ordering of {111} defect arrays in Si nanowires. Stacking faults were found to occur in periodic arrangements corresponding to the 9R rhombohedral and 2H hexagonal polytypes. Cross-sectional imaging was used to establish the origins and strengths of forbidden reflections arising from ordered stacking faults and twinned nanowires.