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A Fully-Integrated All-Digital Outphasing Transmitter for Wireless Communications

ProQuest Dissertations and Theses, 2009
Dissertation
Author: Kwan-Woo Kim
Abstract:
The objective of the proposed research is to present a new all-digital outphasing transmitter IC, a comprehensive explanation of its operation, and its performance characterization. The all-digital transmitter chip leverages flexible digital phase modulators (DPMs) to adaptively compensate for amplifier mismatches. As the DPM uses a digital input to directly modulate the RF phase of each path, the phase control becomes very simple and accurate for power amplifier (PA) gain/phase mismatch compensation. Furthermore, this digital phase modulation scheme also facilitates minimizing the distortion of an RF combiner. It is newly proposed that two distinct digital predistortion algorithms are required for perfect compensation for both PAs and a combiner. All phase calibration values can be adaptively calculated as a function of outphase angle and saved in digital look-up tables to predistort the phase inputs of two DPMs. Various types of PAs and combiners are investigated to further enhance the performance of the outphasing transmitter. These features are implemented in a chip fabricated in a 0.18-µm CMOS process and evaluated with IEEE 802.16e baseband symbols.

iii T ABLE OF C ONTENTS

A CKNOWLEDGEMENTS ......................................................................................................... II

L IST OF T ABLES .................................................................................................................. VI

L IST OF F IGURES ................................................................................................................ VII

S UMMARY ............................................................................................................................ X

C HAPTER I...........................................................................................................................1

C HAPTER II..........................................................................................................................9

2.1

P RINCIPLE OF O UTPHASING A MPLIFICATION ..........................................................9

2.2

C HALLENGES .......................................................................................................12

2.2.1

M ATCHING R EQUIREMENTS AND M ISMATCH E RROR C OMPENSATION ...............12

2.2.2

E FFICIENCY E NHANCEMENT VS .

L INEARITY .....................................................12

2.3

P RIOR A RT ...........................................................................................................13

2.3.1

Q UADRATURE M ODULATOR BASED O UTPHASING T RANSMITTER WITH M ISMATCH C ALIBRATION ..............................................................................................................13

2.3.2

A NALOG P HASE S HIFTER BASED O UTPHASING T RANSMITTER ...........................15

2.3.3

C HIREIX P OWER C OMBINER FOR E FFICIENCY E NHANCEMENT .........................16

C HAPTER III.......................................................................................................................18

3.1

M AIN A RCHITECTURE ............................................................................................18

3.2

S YSTEM R EQUIREMENTS ........................................................................................20

3.3

K EY B UILDING B LOCKS .......................................................................................23

3.3.1

D IGITAL P HASE M ODULATOR .........................................................................23

3.3.2

P OWER A MPLIFIER .........................................................................................29

iv 3.3.3

P OWER C OMBINER .........................................................................................31

3.4

D IGITAL M ISMATCH C OMPENSATION A LGORITHMS ............................................34

3.4.1

F OREGROUND M ISMATCH C OMPENSATION A LGORITHMS ................................36

3.4.2

B ACKGROUND M ISMATCH C OMPENSATION A LGORITHMS ................................40

3.4.3

S IMULATION R ESULTS ....................................................................................41

C HAPTER IV.......................................................................................................................46

4.1.

IC

I MPLEMENTATION ...........................................................................................46

4.2.

B UILDING B LOCKS ...............................................................................................47

4.2.1.

D IGITAL P HASE M ODULATOR .........................................................................47

4.2.2.

V OLTAGE -C ONTROLLED O SCILLATOR .............................................................51

4.2.3.

F REQUENCY S YNTHESIZER ..............................................................................52

4.3.

M EASUREMENT R ESULTS .....................................................................................55

C HAPTER V........................................................................................................................64

5.1.

P OWER C OMBINER ...............................................................................................66

5.2.

D ESIGN C ONSIDERATIONS ....................................................................................72

5.2.1.

E FFICIENCY ...................................................................................................72

5.2.2.

L INEARITY ......................................................................................................80

5.3.

C IRCUIT I MPLEMENTATION ..................................................................................81

5.4.

K EY BUILDING B LOCKS .......................................................................................83

5.4.1.

L OW P OWER D IGITAL P HASE M ODULATOR .....................................................83

5.4.2.

C LASS E

P OWER A MPLIFIER WITH I SOLATED C OMBINER ..................................86

5.4.3.

C LASS D

P OWER A MPLIFIER WITH N ON - ISOLATED C OMBINER .........................86

5.5.

M EASUREMENT R ESULTS .....................................................................................87

v 5.5.1.

M EASUREMENT S ETUP ...................................................................................87

5.5.2.

M EASUREMENT R ESULTS ................................................................................88

C HAPTER VI.......................................................................................................................93

R EFERENCES ......................................................................................................................95

P UBLICATIONS ...................................................................................................................99

V ITA ................................................................................................................................101

vi L IST OF T ABLES

T ABLE 4.1.

P ERFORMANCE SUMMARY OF OUTPHASING MODULATOR ………….………

62

vii L IST OF F IGURES

F IGURE 1.1.

E VOLUTION OF WIRELESS COMMUNICATIONS ...................................................1 F IGURE 1.2.

S IGNAL PROFILE OF OFDM-W IRELESS LAN.

( A )

T IME - DOMAIN SIGNAL WAVEFORM ,

( B )

PDF OF OUTPUT POWER .....................................................................2 F IGURE 1.3.

M AXIMUM EFFICIENCY OF IDEAL C LASS A AND C LASS B

PA S .........................3 F IGURE 1.4.

C OMPARISON OF LINEAR AMPLIFICATION TECHNIQUES ....................................4 F IGURE 1.5.

C OMPARISON OF EFFICIENCY WITH DIFFERENT LINEAR AMPLIFICATION TECHNIQUES .................................................................................................................5

F IGURE 2.1.

O UTPHASING SIGNAL DECOMPOSITION .............................................................9 F IGURE 2.2.

V ECTOR REPRESENTATION OF OUTPHASING SIGNAL DECOMPOSITION ............11 F IGURE 2.3.

C OMBINER ARCHITECTURE : ISOLATED AND NON - ISOLATED COMBINER ..........13 F IGURE 2.4.

C ONVENTIONAL ANALOG OUTPHASING TRANSMITTER WITH I/Q QUADRATURE MODULATORS .............................................................................................................14 F IGURE 2.5.

A NALOG PHASE SHIFTER - BASED OUTPHASING TRANSMITTER .........................15 F IGURE 2.6.

C HIREIX POWER COMBINER ............................................................................17

F IGURE 3.1.

B LOCK DIAGRAM OF PROPOSED ALL - DIGITAL OUTPHASING TRANSMITTER .....19 F IGURE 3.2.

E FFECTS OF NUMBER OF BITS IN DPM ON IEEE

802.16 E MODULATION .........22 F IGURE 3.3.

B LOCK DIAGRAM OF N - BIT DIGITAL PHASE MODULATOR ................................24 F IGURE 3.4.

T IMING DIAGRAM OF 8- BIT DIGITAL PHASE MODULATOR ................................26 F IGURE 3.5.

R ELATIVE PHASE SHIFT CORRESPONDING TO INPUT SIGNALS ..........................27 F IGURE 3.6.

DLL- BASED DIGITAL PHASE MODULATOR ......................................................28 F IGURE 3.7.

B ASIC TOPOLOGY OF C LASS E AMPLIFIER .......................................................30 F IGURE 3.8.

A RCHITECTURE OF GENERAL NON - ISOLATED COMBINER ................................32 F IGURE 3.9.

E RRORS OF OUTPHASING AMPLIFICATION .......................................................35 F IGURE 3.10.

S EQUENCE OF STEPS FOR STATIC MISMATCH COMPENSATION .......................37 F IGURE 3.11.

S EQUENCE OF STEPS FOR DYNAMIC MISMATCH COMPENSATION .

( A )

D YNAMIC ERROR MEASUREMENT WITH TEST VECTORS ,

( B )

D YNAMIC MISMATCH COMPENSATION WITH LOOK - UP TABLES ...............................................................................................40 F IGURE 3.12.

EVM AND SPECTRUM OF OUTPUT SIGNAL BEFORE MISMATCH CALIBRATION . ...................................................................................................................................43 F IGURE 3.13.

S UMMARY OF LOOK - UP TABLES ....................................................................44 F IGURE 3.14.

EVM AND SPECTRUM OF OUTPUT SIGNAL AFTER MISMATCH CALIBRATION ..44

F IGURE 4.1.

B LOCK DIAGRAM OF ALL - DIGITAL OUTPHASING TRANSMITTER ......................47 F IGURE 4.2.

B LOCK DIAGRAM OF PROPOSED 9- BIT DIGITAL PHASE MODULATOR ...............48 F IGURE 4.3.

C IRCUIT IMPLEMENTATION OF 5- BIT DIGITAL PHASE INTERPOLATOR .............49 F IGURE 4.4.

M EASUREMENT RESULTS AND CALIBRATION OF DIGITAL PHASE INTERPOLATOR . ...................................................................................................................................50 F IGURE 4.5.

T IMING DIAGRAM OF 9- BIT DIGITAL PHASE MODULATOR ................................51 F IGURE 4.6.

S CHEMATIC OF ON - CHIP QUADRATURE VCO..................................................52 F IGURE 4.7.

B LOCK DIAGRAM OF INTEGRATED FREQUENCY SYNTHESIZER ........................53

viii F IGURE 4.8.

C HIP MICROPHOTOGRAPH ...............................................................................56 F IGURE 4.9.

PLL MEASUREMENT RESULTS .

( A )

O UTPUT SPECTRUM ,

( B )

P HASE NOISE ......57 F IGURE 4.10.

M EASUREMENT SETUP ..................................................................................58 F IGURE 4.11.

P HASE MODULATED S 1 ( T ) WITH HOLD 1 AND PH_CLK...............................59 F IGURE 4.12.

S PECTRUM OF OUTPUT SIGNAL BEFORE AND AFTER MISMATCH COMPENSATION .

( A )

B EFORE MISMATCH COMPENSATION WITH F B =48

MH Z ,

( B )

A FTER MISMATCH COMPENSATION WITH F B

=80

MH Z ..........................................................61 F IGURE 4.13.

EVM MEASUREMENT AFTER MISMATCH COMPENSATION WITH F B

=80

MH Z . ...................................................................................................................................62

F IGURE 5.1.

W ILKINSON POWER COMBINER .......................................................................65 F IGURE 5.2.

N ON - ISOLATED POWER COMBINER .................................................................65 F IGURE 5.3.

C OMPARISON OF POWER EFFICIENCY WITH DIFFERENT COMBINER AND PA

STRUCTURE ................................................................................................................66 F IGURE 5.4.

N ON - ISOLATED COMBINER WITH TRANSMISSION LINES ..................................67 F IGURE 5.5.

S IMPLE SCHEMATIC OF VM

C LASS D

PA.......................................................70 F IGURE 5.6.

S IMPLE SCHEMATIC OF C LASS E

PA...............................................................70 F IGURE 5.7.

S IMPLE SCHEMATIC OF C LASS F

PA...............................................................70 F IGURE 5.8.

E FFICIENCY COMPARISON BETWEEN ISOLATED AND NON - ISOLATED COMBINER . ...................................................................................................................................71 F IGURE 5.9.

L INEARITY COMPARISON BETWEEN ISOLATED AND NON - ISOLATED COMBINER . ...................................................................................................................................72 F IGURE 5.10.

S CHEMATIC OF VM

C LASS D MODEL WITH NON - ISOLATED COMBINER ........74 F IGURE 5.11.

S IMPLIFIED SCHEMATIC OF VM

C LASS D MODEL WITH NON - ISOLATED COMBINER ..................................................................................................................75 F IGURE 5.12.

E QUIVALENT SCHEMATIC OF VM

C LASS D MODEL WITH NON - ISOLATED COMBINER ..................................................................................................................76 F IGURE 5.13.

E FFICIENCY RESULTS WITH DIFFERENT C P VALUES .......................................78 F IGURE 5.14.

E FFICIENCY RESULTS WITH DIFFERENT R DS VALUES ....................................79 F IGURE 5.15.

E FFICIENCY RESULTS WITH DIFFERENT R 0 VALUES .......................................79 F IGURE 5.16.

E FFICIENCY RESULTS WITH DIFFERENT R Π VALUES .......................................80 F IGURE 5.17.

B LOCK DIAGRAM OF FULLY - INTEGRATED ALL - DIGITAL OUTPHASING TRANSMITTER ............................................................................................................81 F IGURE 5.18.

C HIP MICROGRAPH (F ULLY - INTEGRATED ALL - DIGITAL OUTPHASING TRANSMITTER WITH C LASS E

PA S )............................................................................82 F IGURE 5.19.

C HIP MICROGRAPH (A LL - DIGITAL OUTPHASING TRANSMITTER WITH LPDPM

AND C LASS D

PA S )....................................................................................................82 F IGURE 5.20.

B LOCK DIAGRAM OF PROPOSED LOW POWER DIGITAL PHASE MODULATOR ...84 F IGURE 5.21.

B LOCK DIAGRAM OF PROPOSED LOW POWER DIGITAL PHASE MODULATOR ...85 F IGURE 5.22.

B UILDING BLOCKS FOR LPDPM.

( A )

S CHEMATIC OF TSPC

D- FLIPFLOP ,

( B )

D IGITAL PI.................................................................................................................85 F IGURE 5.23.

S CHEMATIC OF IMPLEMENTED C LASS E

PA S AND COMBINER .......................86 F IGURE 5.24.

IC MEASUREMENT SETUP FOR FULLY - INTEGRATED ALL - DIGITAL OUTPHASING TRANSMITTER WITH C LASS E

PA S .............................................................................87 F IGURE 5.25.

IC MEASUREMENT SETUP FOR ALL - DIGITAL OUTPHASING TRANSMITTER WITH C LASS D

PA S .............................................................................................................88

ix F IGURE 5.26.

O UTPUT POWER AND EFFICIENCY MEASURED WITH DIFFERENT OUTPHASE ANGLE IN OUTPHASING TRANSMITTER WITH C LASS E

PA S .

( A )

O UTPUT POWER ,

( B )

D RAIN EFFICIENCY .....................................................................................................89 F IGURE 5.27.

O UTPUT POWER AND EFFICIENCY MEASURED WITH DIFFERENT OUTPHASE ANGLE IN OUTPHASING TRANSMITTER WITH C LASS D

PA S .

( A )

O UTPUT POWER ,

( B )

D RAIN EFFICIENCY .....................................................................................................90 F IGURE 5.28.

O UTPUT SPECTRUM AND EVM MEASURED IN OUTPHASING TRANSMITTER WITH C LASS E

PA S .

( A )

O UTPUT SPECTRUM ,

( B )

C ONSTELLATION (EVM=-26.7 D B). ...................................................................................................................................91 F IGURE 5.29.

O UTPUT SPECTRUM AND EVM MEASURED IN OUTPHASING TRANSMITTER WITH C LASS D

PA S .

( A )

O UTPUT SPECTRUM ,

( B )

C ONSTELLATION (EVM=-25.5 D B). ...................................................................................................................................92

x

S UMMARY

The objective of the proposed research is to present a new all-digital outphasing transmitter IC, a comprehensive explanation of its operation, and its performance characterization. The all-digital transmitter chip leverages flexible digital phase modulators (DPMs) to adaptively compensate for amplifier mismatches. As the DPM uses a digital input to directly modulate the RF phase of each path, the phase control becomes very simple and accurate for power amplifier (PA) gain/phase mismatch compensation. Furthermore, this digital phase modulation scheme also facilitates minimizing the distortion of an RF combiner. It is newly proposed that two distinct digital predistortion algorithms are required for perfect compensation for both PAs and a combiner. All phase calibration values can be adaptively calculated as a function of outphase angle and saved in digital look-up tables to predistort the phase inputs of two DPMs. Various types of PAs and combiners are investigated to further enhance the performance of the outphasing transmitter. These features are implemented in a chip fabricated in a 0.18-μm CMOS process and evaluated with IEEE 802.16e baseband symbols.

1 C HAPTER I

I NTRODUCTION

The demand for higher data throughput in wireless communications has been increasing at a tremendous rate over the past decade. Figure 1.1 shows the evolution of wireless communication trends with various coverage ranges.

Figure 1.1. Evolution of wireless communications.

As shown in the figure, every new emerging wireless standard requires a higher data rate with more stringent user connectivity. To deal with these requirements, both

2 spectral and power efficiencies are important factors in modern wireless communication for high-speed data connection and long battery life, respectively. However, an intrinsic trade-off exists between these two PA design metrics. To increase the spectral efficiency, baseband signals should have complex I/Q symbols, which require both amplitude and phase modulation. Since most amplitude modulated signals have high peak-to-average-power ratio (PAPR), a substantial back-off is generally needed to ensure adequate amplifier linearity; thus the average power efficiency is significantly degraded. For example, orthogonal frequency division multiplexing (OFDM) is very spectrally efficient and mitigates multi-path fading due to its long symbol duration, but one of the major drawbacks of the OFDM system is its sensitivity to nonlinear distortion due to its wide variation in signal envelope and low average power efficiency. Figure 1.2 shows the time-domain waveform of an IEEE802.11g OFDM- Wireless local area network (LAN) signal and its probability density function (PDF) of output power [1].

(a) (b)

Figure 1.2. Signal profile of OFDM-Wireless LAN. (a) Time-domain signal waveform, (b) PDF of output power.

3 As shown in the figure, the output power of the OFDM signal is much less than the peak output power at most times. However, PAs, which consumes the largest amount of power in a typical wireless transmitter, tend to be most efficient only when delivering peak output power, while the efficiency degrades with reduced output power. Figure 1.3 shows typical linear PA efficiency graphs.

Figure 1.3. Maximum efficiency of ideal Class A and Class B PAs.

Therefore, to support the large PAPR in the OFDM systems, the PAs unfortunately have to spend most of their time in back-off where the efficiency is poor. The average power efficiency of an OFDM system using linear PAs can be calculated by multiplying the PDF of output power by the efficiency profile of linear PA and it is typically much less than 15% in most CMOS PAs; thus most of the system power is dissipated in PA to meet the linearity requirements of an OFDM signal [2].

4 To resolve efficiency degradation problems in linear PAs, various efficiency enhancement technologies have been proposed. Figure 1.4 compares three major linear amplification techniques. A polar transmitter, also called envelope elimination and restoration (EER), is one of the most promising techniques for improving efficiency. Compared to a Class A PA, the polar transmitter demonstrates a much higher power efficiency. The polar transmitter basically operates by converting complex I/Q symbols into envelope and constant envelope phase signals. The constant envelope signal is amplified through a highly efficient nonlinear PA with a separate envelope control path. However, despite the efficiency improvement, the separate amplitude modulation through a low dropout (LDO) regulator, DC/DC converter, ΣΔ modulator, or PWM has significant bandwidth limitation and efficiency degradation problems in commercial wideband systems [3]-[11].

Figure 1.4. Comparison of linear amplification techniques.

5 The outphasing power amplification, also called linear amplification using nonlinear components (LINC), was proposed as another solution that may offer high efficiency with good linearity [12]. LINC eliminates the high linearity demands on a single PA by summing the outputs of two nonlinear PAs via a power combiner to amplify non-constant envelope signals. This technique produces an amplifier with the linearity of a moderate back-off linear PA at an efficiency approaching that of a switching amplifier. Also, the outphasing transmitter, which uses two simple wideband switching PAs, can be a good solution for highly power efficient and wideband operation. Figure 1.5 shows the efficiency comparison of different linear amplification techniques.

Figure 1.5. Comparison of efficiency with different linear amplification techniques.

The power efficiency of a Class A amplifier decreases with output power P out

(relative to its peak value P out,max ) proportional to P out /P out,max . Similarly, for a Class B amplifier, the efficiency varies as (P out /P out,max ) 0.5 . Class AB amplifiers have output power

6 variation intermediate between these values. Thus, there is customarily an inherent trade- off between linearity and efficiency in a typical amplifier design [2]. The peak efficiency of a polar transmitter is much higher than that of linear PAs and overall efficiency is mainly determined by the efficiency of the envelope modulator, such as a LDO and DC/DC converter. Also, the outphasing transmitter can provide comparable efficiency with the polar transmitter through PA and combiner optimization. The efficiency curve of the outphasing transmitter will be analyzed in detail. The goal of this research is to enhance the efficiency at back-off and thus reduce the average power consumption of such systems operating with large PAPR through the outphasing amplification techniques. In this dissertation, a new architecture for an all- digital outphasing transmitter is presented. The transmitter employs a novel DPM, which enables all transmitter blocks other than the switching PAs to operate via digital signals. By modulating the outphase signals digitally, mismatches caused by PAs and the combiner are detected and stored in digital look-up tables for each frequency channel. Furthermore, by modulating phase directly, the proposed outphasing transmitter needs only two kinds of test algorithms for complete mismatch compensation, which is very simple compared to an outphasing transmitter based on a quadrature modulator as used in prior work.

The original contributions and main focus of this dissertation include: 1. Development of a new all-digital outphasing transmitter architecture with detailed system requirements and error compensation algorithms.

7 2. First all-digital outphasing modulator with a 0.18-μm CMOS technology for OFDM signals. 3. First to introduce a fully-integrated all-digital outphasing transmitter IC with thorough PA and combiner analysis. This dissertation is organized as follows: Chapter 1 is an introduction of this dissertation and demonstrates the necessity of highly efficient linear power amplifiers in wireless communications. Following that, the organization of the dissertation is described. In chapter 2, a brief historical background and origin of the problems of an outphasing amplification technique is introduced. In chapter 3, a behavioral model for a new all-digital outphasing transmitter, consisting of dual DPMs and switching power amplifiers, is described in detail. This transmitter architecture not only provides linear amplification of OFDM modulation, but also permits fine phase control for error calibration. The effects of phase quantization on digital modulation error performance are studied. The study confirms the feasibility of an all- digital amplifier approach and demonstrates that modulation specifications can be met using quite modest digital work lengths. Chapter 4 focuses on real circuit implementation of the all-digital outphasing modulator with a 0.18-μm CMOS technology. Each building block is described with its detailed operating principles. Also, the overall modulator IC performances, such as total power consumption, phase noise results of a frequency synthesizer, and modulation errors, are demonstrated. Chapter 5 describes and analyzes the effects of switching power amplifiers on overall outphasing transmitter efficiency. The average system efficiency mainly depends on the characteristics of power amplifiers; thus various nonlinear

8 switching PAs are analyzed numerically in an outphasing transmitter. In addition, a fully- integrated all-digital outphasing transmitter IC is presented to verify the PA analysis. Two types of PAs, Class D and Class E, are implemented and integrated with the outphasing modulator presented in chapter 4. Finally, chapter 6 summarizes the dissertation and provides guidance towards future research possibilities.

9 C HAPTER II

O UTPHASING A MPLIFICATION

2.1 Principle of Outphasing Amplification

The outphasing amplification technique basically operates by representing an amplitude and phase modulated signal, S IN (t), as the difference of two constant amplitude, phase modulated signals, S 1 (t) and S 2 (t) [13]. These two signals can then be amplified separately through high efficiency nonlinear switching PAs and recombined to produce the amplified original signal, as shown in Figure 2.1.

Figure 2.1. Outphasing signal decomposition.

A complex polar representation of the original signal can be written as

10

( ) ( ) ( ) ( ) ( ) c c j t t j t IN I Q IN S t S t j S t e S t e ω φ ω ⋅ + ⎡ ⎤ ⎣ ⎦ ⎡ ⎤ = + ⋅ ⋅ = ⋅ ⎣ ⎦ , (2.1)

where

( ) ( ) ( ) 2 2 IN I Q S t S t S t= + (2.2) ( ) ( ) ( ) 1 Q I S t t tan S t φ − ⎛ ⎞ = ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ . (2.3)

The original signal can also be expressed by a sum of two phase modulated signals as

( ) ( ) ( ) 1 2IN S t S t S t= + (2.4) ( ) ( ) ( ) 1 max c j t t t S t A e ω φ θ⋅ + +⎡ ⎤ ⎣ ⎦ = ⋅ (2.5) ( ) ( ) ( ) 2 max c j t t t S t A e ω φ θ⋅ + −⎡ ⎤ ⎣ ⎦ = ⋅ (2.6) ( ) ( ) ( ) ( ) 1 2OUT IN S t G S t G S t S t= ⋅ = ⋅ + ⎡ ⎤ ⎣ ⎦ , (2.7)

where G is the gain of each PA and θ(t) is the outphase angle given by

( ) ( ) 1 max cos 2 IN S t t A θ − ⎛ ⎞ = ⎜ ⎟ ⎜ ⎟ ⋅ ⎝ ⎠ (2.8)

and (2·A max ) is the peak of the S IN (t) envelope. From (2.5) and (2.6), both S 1 (t) and S 2 (t) have only phase information, φ(t) and θ(t) . φ(t) is the phase of the original baseband symbol and θ(t) is the additional phase modulated angle related to the outphasing amplification. The block, which calculates this

11 outphase angle calculation, is called a signal component separator (SCS). The outphasing decomposition and reconstruction can easily be represented by a vector diagram, as shown in Figure 2.2.

Figure 2.2. Vector representation of outphasing signal decomposition.

For an ideal outphasing amplifier, the two PAs should have identical gain and phase response for linear amplification and operate at saturation, yielding maximum amplifier efficiency. Simultaneously, the power combiner, which is used to combine the output of both PAs, should operate linearly over all the frequency bands of interest with perfect isolation between both inputs. However, both the non-identical responses of PAs and the power combiner’s imperfect isolation distort the output signal of the outphasing transmitter. Thus, compensation algorithms for minimizing such distortion are necessary for a useful practical implementation. In this research, simple digital calibration methods using look-up tables are presented, which replace the conventional quadrature modulator with a handy DPM.

12 2.2 Challenges

Despite the efficiency enhancement, the outphasing topology has not been widely used in commercial amplifiers due to its strict matching requirements both in the phase and amplitude of each path [14][15] and non-isolation distortion and efficiency degradation caused by the RF power combiner [16][17].

2.2.1 Matching Requirements and Mismatch Error Compensation

For an ideal outphasing amplifier, the two PAs should have identical gain and phase response for linear amplification and operate at saturation, yielding maximum amplifier efficiency. Simultaneously, the power combiner, which is used to combine the output of two PAs, should operate linearly over all the frequency bands of interest with perfect isolation between both inputs. However, both the non-identical responses of PAs and the non-isolation properties of a power combiner distort the output signal of the outphasing transmitter. The mathematical analysis to evaluate the effects of the imbalances and the non-isolation distortion on the performance of the outphasing transmitter shows that only a gain imbalance of 0.3~0.4 dB or the phase imbalance of 2~3° can be tolerated [18]. Thus, extremely precise compensation algorithms for minimizing such errors are necessary for a useful practical implementation.

2.2.2 Efficiency Enhancement vs. Linearity

The key advantage of an outphasing system is the ability to maintain a high efficiency and the efficiency mainly depends on the configuration of a power combiner,

13 which adds the outputs of two nonlinear PAs. There are two kinds of combiner architectures, isolated and non-isolated, as shown in Figure 2.3. An isolated combiner, such as a Wilkinson combiner, provides good linearity, but the out-of-phase components of the combined signals are directed to the isolated resistor load and dissipated when the output power decreases. On the contrary, a non-isolated combiner, such as a Chireix combiner, is a lossless combining structure, which provides much higher combining efficiency than the isolated combiner at the cost of linearity due to the lack of isolation. Thus, to take advantage of the high efficiency, an outphasing system requires the use of a non-isolated combiner with the improved linearity through appropriate calibration algorithms.

(a) Isolated combiner (b) Non-isolated combiner

Figure 2.3. Combiner architecture: isolated and non-isolated combiner.

2.3 Prior Art

2.3.1 Quadrature Modulator based Outphasing Transmitter with Mismatch Calibration

Figure 2.4 shows a conventional analog outphasing transmitter based on I/Q quadrature modulators [19]. In the transmitter, the two outphasing signals, S 1 (t) and S 2 (t) ,

14 are modulated separately by I/Q quadrature modulators. Also, a digital error detection block measures any gain and phase mismatches between the two paths and combiner through a demodulation feedback path, and calibrates the errors by the predistortion of digital baseband symbols. The conventional outphasing transmitter consists of many analog blocks, such as baseband filters, I/Q generation blocks, mixers, driver amplifiers, and so on. Those analog blocks make the system bulky and more susceptible to process and temperature variations than digital blocks in integrated circuits.

Figure 2.4. Conventional analog outphasing transmitter with I/Q quadrature modulators.

Several mismatch calibration schemes have been proposed in [20] and [21], but the method of predistorting baseband symbols requires extremely complex calculations in conjunction with a digital-to-analog converter (DAC) and analog quadrature modulator, which may not be suitable for commercial products.

15 2.3.2 Analog Phase Shifter based Outphasing Transmitter

An outphasing transmitter using two analog phase shifters is presented in Figure 2.5 [14]. In the transmitter, the essence of the outphasing modulation techniques lies in the analog phase shifters that vary the phases of the incoming clock with respect to baseband outphase angles. In the baseband DSP block of the transmitter, the input data are coded and mapped according to the in-phase and the quadrature-phase components, and the data are converted into analog signals with baseband filters. Then, the baseband phase control voltage generator of the transmitter generates the output signals, V p (t) and V m (t) , proportional to the outphase angle, φ(t)+θ(t) , φ(t)-θ(t) in (2.5) and (2.6), respectively.

Figure 2.5. Analog phase shifter-based outphasing transmitter.

There are no mixers to upconvert baseband signals to RF or downconvert the RF signals to the baseband for reference feedback signals compared to the quadrature modulator-based outphasing transmitter. Elimination of the analog blocks and the feedback path in the phase-shifter-based outphasing transmitter results in high-speed, wideband operation, as well as no I/Q mismatches. The simple architecture of the

16 transmitter facilitates the phase modulation of the outphasing system and makes it more robust on circuit variations than the previous quadrature modulator-based transmitter. However, the analog control of the phase shifter degrades the accuracy of output phases, and the open loop structure is also not adequate for the flexible calibration of path mismatches and combiner errors.

2.3.3 Chireix Power Combiner for Efficiency Enhancement

A Chireix power combiner, made of λ/4 transmission-line sections with shunt reactances, is a lossless combining structure that offers substantially higher combining efficiencies [22]. In Figure 2.6, the input impedances of the Chireix combiner, Z in1 and Z in2 , can be represented as

[ ] ( ) ( ) ( ) ( ) ( ) 2 L 2 0 in1 2 L 2 L 4 2 2 2 0 0 Z 2 cos Z Re Z 4Z cos sin Z 1 4 cos Z L Z L θ θ θ θ ω ω ⎛ ⎞ ⎜ ⎟ ⎝ ⎠ = ⎛ ⎞ + − ⎜ ⎟ ⎝ ⎠ (2.9) [ ] ( ) ( ) ( ) ( ) ( ) ( ) L 2 0 in1 2 L 2 L 4 2 2 2 0 0 2Z1 sin cos L Z Im Z 4Z cos sin Z 1 4 cos Z L Z L θ θ ω θ θ θ ω ω ⎛ ⎞ − ⎜ ⎟ ⎝ ⎠ = ⎛ ⎞ + − ⎜ ⎟ ⎝ ⎠ (2.10) [ ] ( ) ( ) ( ) ( ) ( ) 2 L 2 0 in2 2 L 2 2 2 L 4 2 0 0 Z 2 cos Z Re Z 4Z cos sin C Z 4 cos C Z Z θ θ θ ω θ ω ⎛ ⎞ ⎜ ⎟ ⎝ ⎠ = ⎛ ⎞ + − ⎜ ⎟ ⎝ ⎠ (2.11)

17 [ ] ( ) ( ) ( ) ( ) ( ) ( ) L 2 0 in2 2 L 2 2 2 L 4 2 0 0 2Z C sin cos Z Im Z 4Z cos sin C Z 4 cos C Z Z ω θ θ θ θ ω θ ω ⎛ ⎞ − − ⎜ ⎟ ⎝ ⎠ = ⎛ ⎞ + − ⎜ ⎟ ⎝ ⎠ . (2.12)

Figure 2.6. Chireix power combiner.

Full document contains 113 pages
Abstract: The objective of the proposed research is to present a new all-digital outphasing transmitter IC, a comprehensive explanation of its operation, and its performance characterization. The all-digital transmitter chip leverages flexible digital phase modulators (DPMs) to adaptively compensate for amplifier mismatches. As the DPM uses a digital input to directly modulate the RF phase of each path, the phase control becomes very simple and accurate for power amplifier (PA) gain/phase mismatch compensation. Furthermore, this digital phase modulation scheme also facilitates minimizing the distortion of an RF combiner. It is newly proposed that two distinct digital predistortion algorithms are required for perfect compensation for both PAs and a combiner. All phase calibration values can be adaptively calculated as a function of outphase angle and saved in digital look-up tables to predistort the phase inputs of two DPMs. Various types of PAs and combiners are investigated to further enhance the performance of the outphasing transmitter. These features are implemented in a chip fabricated in a 0.18-µm CMOS process and evaluated with IEEE 802.16e baseband symbols.